![James Hogan](/assets/img/avatar_default.png)
Back in early 2008, 4KiB stack support was added to reduce memory consumption on workloads with lots of threads, using a separate IRQ stack per CPU to alleviate stack pressure. However the SMP code added a year and a half later didn't set up the IRQ stack when bringing up secondary CPUs, resulting in a crash when SMP is configured with 4KiB stacks, as soon as the first interrupt arrived on a secondary CPU. Fix with calls to irq_ctx_exit()/irq_ctx_exit() when bringing up/down a CPU. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-metag@vger.kernel.org
668 lines
16 KiB
C
668 lines
16 KiB
C
/*
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* Copyright (C) 2009,2010,2011 Imagination Technologies Ltd.
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*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/atomic.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/cache.h>
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#include <linux/profile.h>
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#include <linux/errno.h>
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#include <linux/mm.h>
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#include <linux/err.h>
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#include <linux/cpu.h>
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#include <linux/smp.h>
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#include <linux/seq_file.h>
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#include <linux/irq.h>
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#include <linux/bootmem.h>
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#include <asm/cacheflush.h>
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#include <asm/cachepart.h>
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#include <asm/core_reg.h>
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#include <asm/cpu.h>
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#include <asm/global_lock.h>
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#include <asm/metag_mem.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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#include <asm/setup.h>
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#include <asm/tlbflush.h>
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#include <asm/hwthread.h>
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#include <asm/traps.h>
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#define SYSC_DCPART(n) (SYSC_DCPART0 + SYSC_xCPARTn_STRIDE * (n))
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#define SYSC_ICPART(n) (SYSC_ICPART0 + SYSC_xCPARTn_STRIDE * (n))
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DECLARE_PER_CPU(PTBI, pTBI);
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void *secondary_data_stack;
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/*
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* structures for inter-processor calls
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* - A collection of single bit ipi messages.
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*/
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struct ipi_data {
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spinlock_t lock;
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unsigned long ipi_count;
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unsigned long bits;
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};
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static DEFINE_PER_CPU(struct ipi_data, ipi_data) = {
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.lock = __SPIN_LOCK_UNLOCKED(ipi_data.lock),
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};
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static DEFINE_SPINLOCK(boot_lock);
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static DECLARE_COMPLETION(cpu_running);
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/*
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* "thread" is assumed to be a valid Meta hardware thread ID.
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*/
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static int boot_secondary(unsigned int thread, struct task_struct *idle)
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{
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u32 val;
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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core_reg_write(TXUPC_ID, 0, thread, (unsigned int)secondary_startup);
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core_reg_write(TXUPC_ID, 1, thread, 0);
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/*
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* Give the thread privilege (PSTAT) and clear potentially problematic
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* bits in the process (namely ISTAT, CBMarker, CBMarkerI, LSM_STEP).
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*/
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core_reg_write(TXUCT_ID, TXSTATUS_REGNUM, thread, TXSTATUS_PSTAT_BIT);
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/* Clear the minim enable bit. */
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val = core_reg_read(TXUCT_ID, TXPRIVEXT_REGNUM, thread);
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core_reg_write(TXUCT_ID, TXPRIVEXT_REGNUM, thread, val & ~0x80);
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/*
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* set the ThreadEnable bit (0x1) in the TXENABLE register
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* for the specified thread - off it goes!
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*/
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val = core_reg_read(TXUCT_ID, TXENABLE_REGNUM, thread);
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core_reg_write(TXUCT_ID, TXENABLE_REGNUM, thread, val | 0x1);
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return 0;
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}
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/**
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* describe_cachepart_change: describe a change to cache partitions.
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* @thread: Hardware thread number.
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* @label: Label of cache type, e.g. "dcache" or "icache".
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* @sz: Total size of the cache.
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* @old: Old cache partition configuration (*CPART* register).
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* @new: New cache partition configuration (*CPART* register).
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*
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* If the cache partition has changed, prints a message to the log describing
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* those changes.
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*/
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static void describe_cachepart_change(unsigned int thread, const char *label,
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unsigned int sz, unsigned int old,
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unsigned int new)
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{
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unsigned int lor1, land1, gor1, gand1;
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unsigned int lor2, land2, gor2, gand2;
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unsigned int diff = old ^ new;
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if (!diff)
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return;
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pr_info("Thread %d: %s partition changed:", thread, label);
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if (diff & (SYSC_xCPARTL_OR_BITS | SYSC_xCPARTL_AND_BITS)) {
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lor1 = (old & SYSC_xCPARTL_OR_BITS) >> SYSC_xCPARTL_OR_S;
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lor2 = (new & SYSC_xCPARTL_OR_BITS) >> SYSC_xCPARTL_OR_S;
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land1 = (old & SYSC_xCPARTL_AND_BITS) >> SYSC_xCPARTL_AND_S;
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land2 = (new & SYSC_xCPARTL_AND_BITS) >> SYSC_xCPARTL_AND_S;
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pr_cont(" L:%#x+%#x->%#x+%#x",
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(lor1 * sz) >> 4,
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((land1 + 1) * sz) >> 4,
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(lor2 * sz) >> 4,
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((land2 + 1) * sz) >> 4);
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}
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if (diff & (SYSC_xCPARTG_OR_BITS | SYSC_xCPARTG_AND_BITS)) {
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gor1 = (old & SYSC_xCPARTG_OR_BITS) >> SYSC_xCPARTG_OR_S;
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gor2 = (new & SYSC_xCPARTG_OR_BITS) >> SYSC_xCPARTG_OR_S;
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gand1 = (old & SYSC_xCPARTG_AND_BITS) >> SYSC_xCPARTG_AND_S;
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gand2 = (new & SYSC_xCPARTG_AND_BITS) >> SYSC_xCPARTG_AND_S;
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pr_cont(" G:%#x+%#x->%#x+%#x",
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(gor1 * sz) >> 4,
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((gand1 + 1) * sz) >> 4,
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(gor2 * sz) >> 4,
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((gand2 + 1) * sz) >> 4);
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}
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if (diff & SYSC_CWRMODE_BIT)
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pr_cont(" %sWR",
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(new & SYSC_CWRMODE_BIT) ? "+" : "-");
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if (diff & SYSC_DCPART_GCON_BIT)
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pr_cont(" %sGCOn",
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(new & SYSC_DCPART_GCON_BIT) ? "+" : "-");
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pr_cont("\n");
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}
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/**
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* setup_smp_cache: ensure cache coherency for new SMP thread.
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* @thread: New hardware thread number.
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*
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* Ensures that coherency is enabled and that the threads share the same cache
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* partitions.
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*/
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static void setup_smp_cache(unsigned int thread)
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{
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unsigned int this_thread, lflags;
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unsigned int dcsz, dcpart_this, dcpart_old, dcpart_new;
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unsigned int icsz, icpart_old, icpart_new;
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/*
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* Copy over the current thread's cache partition configuration to the
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* new thread so that they share cache partitions.
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*/
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__global_lock2(lflags);
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this_thread = hard_processor_id();
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/* Share dcache partition */
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dcpart_this = metag_in32(SYSC_DCPART(this_thread));
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dcpart_old = metag_in32(SYSC_DCPART(thread));
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dcpart_new = dcpart_this;
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#if PAGE_OFFSET < LINGLOBAL_BASE
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/*
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* For the local data cache to be coherent the threads must also have
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* GCOn enabled.
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*/
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dcpart_new |= SYSC_DCPART_GCON_BIT;
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metag_out32(dcpart_new, SYSC_DCPART(this_thread));
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#endif
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metag_out32(dcpart_new, SYSC_DCPART(thread));
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/* Share icache partition too */
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icpart_new = metag_in32(SYSC_ICPART(this_thread));
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icpart_old = metag_in32(SYSC_ICPART(thread));
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metag_out32(icpart_new, SYSC_ICPART(thread));
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__global_unlock2(lflags);
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/*
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* Log if the cache partitions were altered so the user is aware of any
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* potential unintentional cache wastage.
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*/
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dcsz = get_dcache_size();
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icsz = get_dcache_size();
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describe_cachepart_change(this_thread, "dcache", dcsz,
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dcpart_this, dcpart_new);
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describe_cachepart_change(thread, "dcache", dcsz,
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dcpart_old, dcpart_new);
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describe_cachepart_change(thread, "icache", icsz,
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icpart_old, icpart_new);
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}
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int __cpu_up(unsigned int cpu, struct task_struct *idle)
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{
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unsigned int thread = cpu_2_hwthread_id[cpu];
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int ret;
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load_pgd(swapper_pg_dir, thread);
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flush_tlb_all();
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setup_smp_cache(thread);
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/*
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* Tell the secondary CPU where to find its idle thread's stack.
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*/
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secondary_data_stack = task_stack_page(idle);
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wmb();
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/*
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* Now bring the CPU into our world.
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*/
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ret = boot_secondary(thread, idle);
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if (ret == 0) {
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/*
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* CPU was successfully started, wait for it
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* to come online or time out.
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*/
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wait_for_completion_timeout(&cpu_running,
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msecs_to_jiffies(1000));
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if (!cpu_online(cpu))
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ret = -EIO;
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}
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secondary_data_stack = NULL;
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if (ret) {
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pr_crit("CPU%u: processor failed to boot\n", cpu);
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/*
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* FIXME: We need to clean up the new idle thread. --rmk
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*/
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}
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return ret;
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}
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#ifdef CONFIG_HOTPLUG_CPU
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/*
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* __cpu_disable runs on the processor to be shutdown.
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*/
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int __cpu_disable(void)
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{
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unsigned int cpu = smp_processor_id();
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/*
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* Take this CPU offline. Once we clear this, we can't return,
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* and we must not schedule until we're ready to give up the cpu.
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*/
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set_cpu_online(cpu, false);
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/*
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* OK - migrate IRQs away from this CPU
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*/
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migrate_irqs();
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/*
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* Flush user cache and TLB mappings, and then remove this CPU
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* from the vm mask set of all processes.
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*/
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flush_cache_all();
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local_flush_tlb_all();
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clear_tasks_mm_cpumask(cpu);
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return 0;
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}
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/*
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* called on the thread which is asking for a CPU to be shutdown -
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* waits until shutdown has completed, or it is timed out.
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*/
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void __cpu_die(unsigned int cpu)
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{
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if (!cpu_wait_death(cpu, 1))
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pr_err("CPU%u: unable to kill\n", cpu);
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}
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/*
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* Called from the idle thread for the CPU which has been shutdown.
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*
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* Note that we do not return from this function. If this cpu is
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* brought online again it will need to run secondary_startup().
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*/
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void cpu_die(void)
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{
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local_irq_disable();
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idle_task_exit();
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irq_ctx_exit(smp_processor_id());
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(void)cpu_report_death();
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asm ("XOR TXENABLE, D0Re0,D0Re0\n");
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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/*
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* Called by both boot and secondaries to move global data into
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* per-processor storage.
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*/
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void smp_store_cpu_info(unsigned int cpuid)
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{
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struct cpuinfo_metag *cpu_info = &per_cpu(cpu_data, cpuid);
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cpu_info->loops_per_jiffy = loops_per_jiffy;
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}
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/*
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* This is the secondary CPU boot entry. We're using this CPUs
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* idle thread stack and the global page tables.
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*/
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asmlinkage void secondary_start_kernel(void)
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{
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struct mm_struct *mm = &init_mm;
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unsigned int cpu = smp_processor_id();
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/*
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* All kernel threads share the same mm context; grab a
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* reference and switch to it.
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*/
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atomic_inc(&mm->mm_users);
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atomic_inc(&mm->mm_count);
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current->active_mm = mm;
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cpumask_set_cpu(cpu, mm_cpumask(mm));
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enter_lazy_tlb(mm, current);
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local_flush_tlb_all();
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/*
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* TODO: Some day it might be useful for each Linux CPU to
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* have its own TBI structure. That would allow each Linux CPU
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* to run different interrupt handlers for the same IRQ
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* number.
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*
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* For now, simply copying the pointer to the boot CPU's TBI
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* structure is sufficient because we always want to run the
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* same interrupt handler whatever CPU takes the interrupt.
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*/
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per_cpu(pTBI, cpu) = __TBI(TBID_ISTAT_BIT);
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if (!per_cpu(pTBI, cpu))
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panic("No TBI found!");
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per_cpu_trap_init(cpu);
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irq_ctx_init(cpu);
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preempt_disable();
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setup_priv();
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notify_cpu_starting(cpu);
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pr_info("CPU%u (thread %u): Booted secondary processor\n",
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cpu, cpu_2_hwthread_id[cpu]);
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calibrate_delay();
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smp_store_cpu_info(cpu);
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/*
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* OK, now it's safe to let the boot CPU continue
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*/
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set_cpu_online(cpu, true);
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complete(&cpu_running);
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/*
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* Enable local interrupts.
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*/
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tbi_startup_interrupt(TBID_SIGNUM_TRT);
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local_irq_enable();
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/*
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* OK, it's off to the idle thread for us
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*/
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cpu_startup_entry(CPUHP_ONLINE);
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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int cpu;
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unsigned long bogosum = 0;
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for_each_online_cpu(cpu)
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bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
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pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
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num_online_cpus(),
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bogosum / (500000/HZ),
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(bogosum / (5000/HZ)) % 100);
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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unsigned int cpu = smp_processor_id();
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init_new_context(current, &init_mm);
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current_thread_info()->cpu = cpu;
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smp_store_cpu_info(cpu);
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init_cpu_present(cpu_possible_mask);
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}
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void __init smp_prepare_boot_cpu(void)
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{
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unsigned int cpu = smp_processor_id();
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per_cpu(pTBI, cpu) = __TBI(TBID_ISTAT_BIT);
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if (!per_cpu(pTBI, cpu))
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panic("No TBI found!");
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}
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static void smp_cross_call(cpumask_t callmap, enum ipi_msg_type msg);
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static void send_ipi_message(const struct cpumask *mask, enum ipi_msg_type msg)
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{
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unsigned long flags;
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unsigned int cpu;
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cpumask_t map;
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cpumask_clear(&map);
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local_irq_save(flags);
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for_each_cpu(cpu, mask) {
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struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
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spin_lock(&ipi->lock);
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/*
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* KICK interrupts are queued in hardware so we'll get
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* multiple interrupts if we call smp_cross_call()
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* multiple times for one msg. The problem is that we
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* only have one bit for each message - we can't queue
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* them in software.
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*
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* The first time through ipi_handler() we'll clear
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* the msg bit, having done all the work. But when we
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* return we'll get _another_ interrupt (and another,
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* and another until we've handled all the queued
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* KICKs). Running ipi_handler() when there's no work
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* to do is bad because that's how kick handler
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* chaining detects who the KICK was intended for.
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* See arch/metag/kernel/kick.c for more details.
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*
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* So only add 'cpu' to 'map' if we haven't already
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* queued a KICK interrupt for 'msg'.
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*/
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if (!(ipi->bits & (1 << msg))) {
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ipi->bits |= 1 << msg;
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cpumask_set_cpu(cpu, &map);
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}
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spin_unlock(&ipi->lock);
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}
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/*
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* Call the platform specific cross-CPU call function.
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*/
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smp_cross_call(map, msg);
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local_irq_restore(flags);
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}
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void arch_send_call_function_ipi_mask(const struct cpumask *mask)
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{
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send_ipi_message(mask, IPI_CALL_FUNC);
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}
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void arch_send_call_function_single_ipi(int cpu)
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{
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send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
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}
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void show_ipi_list(struct seq_file *p)
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{
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unsigned int cpu;
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seq_puts(p, "IPI:");
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for_each_present_cpu(cpu)
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seq_printf(p, " %10lu", per_cpu(ipi_data, cpu).ipi_count);
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seq_putc(p, '\n');
|
|
}
|
|
|
|
static DEFINE_SPINLOCK(stop_lock);
|
|
|
|
/*
|
|
* Main handler for inter-processor interrupts
|
|
*
|
|
* For Meta, the ipimask now only identifies a single
|
|
* category of IPI (Bit 1 IPIs have been replaced by a
|
|
* different mechanism):
|
|
*
|
|
* Bit 0 - Inter-processor function call
|
|
*/
|
|
static int do_IPI(void)
|
|
{
|
|
unsigned int cpu = smp_processor_id();
|
|
struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
|
|
unsigned long msgs, nextmsg;
|
|
int handled = 0;
|
|
|
|
ipi->ipi_count++;
|
|
|
|
spin_lock(&ipi->lock);
|
|
msgs = ipi->bits;
|
|
nextmsg = msgs & -msgs;
|
|
ipi->bits &= ~nextmsg;
|
|
spin_unlock(&ipi->lock);
|
|
|
|
if (nextmsg) {
|
|
handled = 1;
|
|
|
|
nextmsg = ffz(~nextmsg);
|
|
switch (nextmsg) {
|
|
case IPI_RESCHEDULE:
|
|
scheduler_ipi();
|
|
break;
|
|
|
|
case IPI_CALL_FUNC:
|
|
generic_smp_call_function_interrupt();
|
|
break;
|
|
|
|
default:
|
|
pr_crit("CPU%u: Unknown IPI message 0x%lx\n",
|
|
cpu, nextmsg);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return handled;
|
|
}
|
|
|
|
void smp_send_reschedule(int cpu)
|
|
{
|
|
send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
|
|
}
|
|
|
|
static void stop_this_cpu(void *data)
|
|
{
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
if (system_state == SYSTEM_BOOTING ||
|
|
system_state == SYSTEM_RUNNING) {
|
|
spin_lock(&stop_lock);
|
|
pr_crit("CPU%u: stopping\n", cpu);
|
|
dump_stack();
|
|
spin_unlock(&stop_lock);
|
|
}
|
|
|
|
set_cpu_online(cpu, false);
|
|
|
|
local_irq_disable();
|
|
|
|
hard_processor_halt(HALT_OK);
|
|
}
|
|
|
|
void smp_send_stop(void)
|
|
{
|
|
smp_call_function(stop_this_cpu, NULL, 0);
|
|
}
|
|
|
|
/*
|
|
* not supported here
|
|
*/
|
|
int setup_profiling_timer(unsigned int multiplier)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* We use KICKs for inter-processor interrupts.
|
|
*
|
|
* For every CPU in "callmap" the IPI data must already have been
|
|
* stored in that CPU's "ipi_data" member prior to calling this
|
|
* function.
|
|
*/
|
|
static void kick_raise_softirq(cpumask_t callmap, unsigned int irq)
|
|
{
|
|
int cpu;
|
|
|
|
for_each_cpu(cpu, &callmap) {
|
|
unsigned int thread;
|
|
|
|
thread = cpu_2_hwthread_id[cpu];
|
|
|
|
BUG_ON(thread == BAD_HWTHREAD_ID);
|
|
|
|
metag_out32(1, T0KICKI + (thread * TnXKICK_STRIDE));
|
|
}
|
|
}
|
|
|
|
static TBIRES ipi_handler(TBIRES State, int SigNum, int Triggers,
|
|
int Inst, PTBI pTBI, int *handled)
|
|
{
|
|
*handled = do_IPI();
|
|
|
|
return State;
|
|
}
|
|
|
|
static struct kick_irq_handler ipi_irq = {
|
|
.func = ipi_handler,
|
|
};
|
|
|
|
static void smp_cross_call(cpumask_t callmap, enum ipi_msg_type msg)
|
|
{
|
|
kick_raise_softirq(callmap, 1);
|
|
}
|
|
|
|
static inline unsigned int get_core_count(void)
|
|
{
|
|
int i;
|
|
unsigned int ret = 0;
|
|
|
|
for (i = 0; i < CONFIG_NR_CPUS; i++) {
|
|
if (core_reg_read(TXUCT_ID, TXENABLE_REGNUM, i))
|
|
ret++;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Initialise the CPU possible map early - this describes the CPUs
|
|
* which may be present or become present in the system.
|
|
*/
|
|
void __init smp_init_cpus(void)
|
|
{
|
|
unsigned int i, ncores = get_core_count();
|
|
|
|
/* If no hwthread_map early param was set use default mapping */
|
|
for (i = 0; i < NR_CPUS; i++)
|
|
if (cpu_2_hwthread_id[i] == BAD_HWTHREAD_ID) {
|
|
cpu_2_hwthread_id[i] = i;
|
|
hwthread_id_2_cpu[i] = i;
|
|
}
|
|
|
|
for (i = 0; i < ncores; i++)
|
|
set_cpu_possible(i, true);
|
|
|
|
kick_register_func(&ipi_irq);
|
|
}
|