126 lines
3.5 KiB
Plaintext
126 lines
3.5 KiB
Plaintext
Qualcomm Technology Inc. ADSP Peripheral Image Loader
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This document defines the binding for a component that loads and boots firmware
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on the Qualcomm Technology Inc. ADSP Hexagon core.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be one of:
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"qcom,sdm845-adsp-pil"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: must specify the base address and size of the qdsp6ss register
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- interrupts-extended:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: must list the watchdog, fatal IRQs ready, handover and
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stop-ack IRQs
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- interrupt-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of 8 phandle and clock specifier pairs for the adsp.
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: List of clock input name strings sorted in the same
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order as the clocks property. Definition must have
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"xo", "sway_cbcr", "lpass_ahbs_aon_cbcr",
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"lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep"
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and "qdsp6ss_core".
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- power-domains:
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Usage: required
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Value type: <phandle>
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Definition: reference to cx power domain node.
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- resets:
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Usage: required
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Value type: <phandle>
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Definition: reference to the list of 2 reset-controller for the adsp.
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- reset-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "pdc_sync" and "cc_lpass"
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- qcom,halt-regs:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: a phandle reference to a syscon representing TCSR followed
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by the offset within syscon for lpass halt register.
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- memory-region:
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Usage: required
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Value type: <phandle>
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Definition: reference to the reserved-memory for the ADSP
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- qcom,smem-states:
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Usage: required
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Value type: <phandle>
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Definition: reference to the smem state for requesting the ADSP to
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shut down
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- qcom,smem-state-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "stop"
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= SUBNODES
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The adsp node may have an subnode named "glink-edge" that describes the
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communication edge, channels and devices related to the ADSP.
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See ../soc/qcom/qcom,glink.txt for details on how to describe these.
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= EXAMPLE
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The following example describes the resources needed to boot control the
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ADSP, as it is found on SDM845 boards.
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remoteproc@17300000 {
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compatible = "qcom,sdm845-adsp-pil";
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reg = <0x17300000 0x40c>;
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interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_LPASS_SWAY_CLK>,
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<&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
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<&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
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<&lpasscc LPASS_QDSP6SS_XO_CLK>,
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<&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
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<&lpasscc LPASS_QDSP6SS_CORE_CLK>;
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clock-names = "xo", "sway_cbcr",
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"lpass_ahbs_aon_cbcr",
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"lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
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"qdsp6ss_sleep", "qdsp6ss_core";
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power-domains = <&rpmhpd SDM845_CX>;
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resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
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<&aoss_reset AOSS_CC_LPASS_RESTART>;
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reset-names = "pdc_sync", "cc_lpass";
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qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
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memory-region = <&pil_adsp_mem>;
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qcom,smem-states = <&adsp_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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};
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