![Lucas Stach](/assets/img/avatar_default.png)
Using the IOMMU API to manage the internal GPU MMU has been an historical accident and it keeps getting in the way, as well as entangling the driver with the inner workings of the IOMMU subsystem. Clean this up by removing the usage of iommu_domain, which is the last piece linking etnaviv to the IOMMU subsystem. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
198 lines
5.3 KiB
C
198 lines
5.3 KiB
C
/*
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* Copyright (C) 2014 Christian Gmeiner <christian.gmeiner@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/platform_device.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include <linux/bitops.h>
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#include "etnaviv_gpu.h"
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#include "etnaviv_mmu.h"
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#include "etnaviv_iommu.h"
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#include "state_hi.xml.h"
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#define PT_SIZE SZ_2M
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#define PT_ENTRIES (PT_SIZE / sizeof(u32))
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#define GPU_MEM_START 0x80000000
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struct etnaviv_iommuv1_domain {
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struct etnaviv_iommu_domain base;
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u32 *pgtable_cpu;
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dma_addr_t pgtable_dma;
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};
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static struct etnaviv_iommuv1_domain *
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to_etnaviv_domain(struct etnaviv_iommu_domain *domain)
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{
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return container_of(domain, struct etnaviv_iommuv1_domain, base);
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}
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static int __etnaviv_iommu_init(struct etnaviv_iommuv1_domain *etnaviv_domain)
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{
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u32 *p;
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int i;
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etnaviv_domain->base.bad_page_cpu = dma_alloc_coherent(
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etnaviv_domain->base.dev,
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SZ_4K,
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&etnaviv_domain->base.bad_page_dma,
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GFP_KERNEL);
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if (!etnaviv_domain->base.bad_page_cpu)
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return -ENOMEM;
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p = etnaviv_domain->base.bad_page_cpu;
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for (i = 0; i < SZ_4K / 4; i++)
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*p++ = 0xdead55aa;
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etnaviv_domain->pgtable_cpu =
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dma_alloc_coherent(etnaviv_domain->base.dev, PT_SIZE,
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&etnaviv_domain->pgtable_dma,
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GFP_KERNEL);
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if (!etnaviv_domain->pgtable_cpu) {
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dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->base.bad_page_cpu,
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etnaviv_domain->base.bad_page_dma);
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return -ENOMEM;
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}
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for (i = 0; i < PT_ENTRIES; i++)
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etnaviv_domain->pgtable_cpu[i] =
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etnaviv_domain->base.bad_page_dma;
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return 0;
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}
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static void etnaviv_iommuv1_domain_free(struct etnaviv_iommu_domain *domain)
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{
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struct etnaviv_iommuv1_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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dma_free_coherent(etnaviv_domain->base.dev, PT_SIZE,
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etnaviv_domain->pgtable_cpu,
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etnaviv_domain->pgtable_dma);
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dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->base.bad_page_cpu,
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etnaviv_domain->base.bad_page_dma);
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kfree(etnaviv_domain);
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}
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static int etnaviv_iommuv1_map(struct etnaviv_iommu_domain *domain,
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unsigned long iova, phys_addr_t paddr,
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size_t size, int prot)
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{
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struct etnaviv_iommuv1_domain *etnaviv_domain = to_etnaviv_domain(domain);
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unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
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if (size != SZ_4K)
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return -EINVAL;
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etnaviv_domain->pgtable_cpu[index] = paddr;
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return 0;
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}
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static size_t etnaviv_iommuv1_unmap(struct etnaviv_iommu_domain *domain,
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unsigned long iova, size_t size)
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{
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struct etnaviv_iommuv1_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
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if (size != SZ_4K)
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return -EINVAL;
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etnaviv_domain->pgtable_cpu[index] = etnaviv_domain->base.bad_page_dma;
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return SZ_4K;
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}
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static size_t etnaviv_iommuv1_dump_size(struct etnaviv_iommu_domain *domain)
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{
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return PT_SIZE;
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}
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static void etnaviv_iommuv1_dump(struct etnaviv_iommu_domain *domain, void *buf)
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{
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struct etnaviv_iommuv1_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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memcpy(buf, etnaviv_domain->pgtable_cpu, PT_SIZE);
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}
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void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_iommuv1_domain *etnaviv_domain =
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to_etnaviv_domain(gpu->mmu->domain);
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u32 pgtable;
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/* set base addresses */
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
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/* set page table address in MC */
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pgtable = (u32)etnaviv_domain->pgtable_dma;
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gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable);
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gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable);
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gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable);
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gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable);
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gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable);
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}
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const struct etnaviv_iommu_domain_ops etnaviv_iommuv1_ops = {
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.free = etnaviv_iommuv1_domain_free,
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.map = etnaviv_iommuv1_map,
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.unmap = etnaviv_iommuv1_unmap,
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.dump_size = etnaviv_iommuv1_dump_size,
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.dump = etnaviv_iommuv1_dump,
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};
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struct etnaviv_iommu_domain *
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etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_iommuv1_domain *etnaviv_domain;
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struct etnaviv_iommu_domain *domain;
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int ret;
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etnaviv_domain = kzalloc(sizeof(*etnaviv_domain), GFP_KERNEL);
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if (!etnaviv_domain)
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return NULL;
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domain = &etnaviv_domain->base;
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domain->dev = gpu->dev;
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domain->base = GPU_MEM_START;
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domain->size = PT_ENTRIES * SZ_4K;
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domain->ops = &etnaviv_iommuv1_ops;
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ret = __etnaviv_iommu_init(etnaviv_domain);
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if (ret)
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goto out_free;
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return &etnaviv_domain->base;
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out_free:
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kfree(etnaviv_domain);
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return NULL;
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}
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