![Dan Carpenter](/assets/img/avatar_default.png)
If the kmalloc() fails then we dereference "state" when we set
"state->zpos".
Fixes: 3dfeb631a1
("drm/omap: Rework the rotation-on-crtc hack")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
712 lines
19 KiB
C
712 lines
19 KiB
C
/*
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* drivers/gpu/drm/omapdrm/omap_crtc.c
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*
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* Copyright (C) 2011 Texas Instruments
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* Author: Rob Clark <rob@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_mode.h>
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#include <drm/drm_plane_helper.h>
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#include "omap_drv.h"
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#define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
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struct omap_crtc_state {
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/* Must be first. */
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struct drm_crtc_state base;
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/* Shadow values for legacy userspace support. */
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unsigned int rotation;
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unsigned int zpos;
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};
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#define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
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struct omap_crtc {
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struct drm_crtc base;
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const char *name;
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enum omap_channel channel;
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struct videomode vm;
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bool ignore_digit_sync_lost;
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bool enabled;
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bool pending;
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wait_queue_head_t pending_wait;
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struct drm_pending_vblank_event *event;
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};
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/* -----------------------------------------------------------------------------
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* Helper Functions
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*/
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struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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return &omap_crtc->vm;
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}
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enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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return omap_crtc->channel;
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}
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static bool omap_crtc_is_pending(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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unsigned long flags;
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bool pending;
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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pending = omap_crtc->pending;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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return pending;
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}
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int omap_crtc_wait_pending(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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/*
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* Timeout is set to a "sufficiently" high value, which should cover
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* a single frame refresh even on slower displays.
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*/
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return wait_event_timeout(omap_crtc->pending_wait,
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!omap_crtc_is_pending(crtc),
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msecs_to_jiffies(250));
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}
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/* -----------------------------------------------------------------------------
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* DSS Manager Functions
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*/
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/*
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* Manager-ops, callbacks from output when they need to configure
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* the upstream part of the video pipe.
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*
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* Most of these we can ignore until we add support for command-mode
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* panels.. for video-mode the crtc-helpers already do an adequate
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* job of sequencing the setup of the video pipe in the proper order
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*/
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/* ovl-mgr-id -> crtc */
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static struct omap_crtc *omap_crtcs[8];
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static struct omap_dss_device *omap_crtc_output[8];
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/* we can probably ignore these until we support command-mode panels: */
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static int omap_crtc_dss_connect(enum omap_channel channel,
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struct omap_dss_device *dst)
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{
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const struct dispc_ops *dispc_ops = dispc_get_ops();
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if (omap_crtc_output[channel])
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return -EINVAL;
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if ((dispc_ops->mgr_get_supported_outputs(channel) & dst->id) == 0)
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return -EINVAL;
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omap_crtc_output[channel] = dst;
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dst->dispc_channel_connected = true;
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return 0;
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}
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static void omap_crtc_dss_disconnect(enum omap_channel channel,
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struct omap_dss_device *dst)
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{
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omap_crtc_output[channel] = NULL;
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dst->dispc_channel_connected = false;
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}
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static void omap_crtc_dss_start_update(enum omap_channel channel)
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{
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}
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/* Called only from the encoder enable/disable and suspend/resume handlers. */
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static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
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{
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struct drm_device *dev = crtc->dev;
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struct omap_drm_private *priv = dev->dev_private;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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enum omap_channel channel = omap_crtc->channel;
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struct omap_irq_wait *wait;
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u32 framedone_irq, vsync_irq;
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int ret;
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if (WARN_ON(omap_crtc->enabled == enable))
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return;
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if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) {
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priv->dispc_ops->mgr_enable(channel, enable);
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omap_crtc->enabled = enable;
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return;
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}
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if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
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/*
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* Digit output produces some sync lost interrupts during the
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* first frame when enabling, so we need to ignore those.
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*/
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omap_crtc->ignore_digit_sync_lost = true;
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}
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framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(channel);
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vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(channel);
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if (enable) {
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wait = omap_irq_wait_init(dev, vsync_irq, 1);
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} else {
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/*
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* When we disable the digit output, we need to wait for
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* FRAMEDONE to know that DISPC has finished with the output.
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*
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* OMAP2/3 does not have FRAMEDONE irq for digit output, and in
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* that case we need to use vsync interrupt, and wait for both
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* even and odd frames.
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*/
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if (framedone_irq)
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wait = omap_irq_wait_init(dev, framedone_irq, 1);
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else
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wait = omap_irq_wait_init(dev, vsync_irq, 2);
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}
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priv->dispc_ops->mgr_enable(channel, enable);
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omap_crtc->enabled = enable;
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ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
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if (ret) {
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dev_err(dev->dev, "%s: timeout waiting for %s\n",
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omap_crtc->name, enable ? "enable" : "disable");
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}
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if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
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omap_crtc->ignore_digit_sync_lost = false;
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/* make sure the irq handler sees the value above */
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mb();
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}
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}
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static int omap_crtc_dss_enable(enum omap_channel channel)
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{
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struct omap_crtc *omap_crtc = omap_crtcs[channel];
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struct omap_drm_private *priv = omap_crtc->base.dev->dev_private;
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priv->dispc_ops->mgr_set_timings(omap_crtc->channel, &omap_crtc->vm);
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omap_crtc_set_enabled(&omap_crtc->base, true);
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return 0;
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}
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static void omap_crtc_dss_disable(enum omap_channel channel)
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{
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struct omap_crtc *omap_crtc = omap_crtcs[channel];
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omap_crtc_set_enabled(&omap_crtc->base, false);
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}
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static void omap_crtc_dss_set_timings(enum omap_channel channel,
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const struct videomode *vm)
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{
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struct omap_crtc *omap_crtc = omap_crtcs[channel];
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DBG("%s", omap_crtc->name);
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omap_crtc->vm = *vm;
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}
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static void omap_crtc_dss_set_lcd_config(enum omap_channel channel,
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const struct dss_lcd_mgr_config *config)
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{
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struct omap_crtc *omap_crtc = omap_crtcs[channel];
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struct omap_drm_private *priv = omap_crtc->base.dev->dev_private;
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DBG("%s", omap_crtc->name);
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priv->dispc_ops->mgr_set_lcd_config(omap_crtc->channel, config);
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}
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static int omap_crtc_dss_register_framedone(
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enum omap_channel channel,
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void (*handler)(void *), void *data)
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{
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return 0;
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}
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static void omap_crtc_dss_unregister_framedone(
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enum omap_channel channel,
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void (*handler)(void *), void *data)
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{
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}
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static const struct dss_mgr_ops mgr_ops = {
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.connect = omap_crtc_dss_connect,
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.disconnect = omap_crtc_dss_disconnect,
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.start_update = omap_crtc_dss_start_update,
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.enable = omap_crtc_dss_enable,
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.disable = omap_crtc_dss_disable,
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.set_timings = omap_crtc_dss_set_timings,
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.set_lcd_config = omap_crtc_dss_set_lcd_config,
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.register_framedone_handler = omap_crtc_dss_register_framedone,
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.unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
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};
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/* -----------------------------------------------------------------------------
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* Setup, Flush and Page Flip
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*/
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void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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if (omap_crtc->ignore_digit_sync_lost) {
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irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
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if (!irqstatus)
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return;
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}
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DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
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}
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void omap_crtc_vblank_irq(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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struct drm_device *dev = omap_crtc->base.dev;
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struct omap_drm_private *priv = dev->dev_private;
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bool pending;
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spin_lock(&crtc->dev->event_lock);
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/*
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* If the dispc is busy we're racing the flush operation. Try again on
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* the next vblank interrupt.
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*/
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if (priv->dispc_ops->mgr_go_busy(omap_crtc->channel)) {
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spin_unlock(&crtc->dev->event_lock);
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return;
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}
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/* Send the vblank event if one has been requested. */
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if (omap_crtc->event) {
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drm_crtc_send_vblank_event(crtc, omap_crtc->event);
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omap_crtc->event = NULL;
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}
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pending = omap_crtc->pending;
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omap_crtc->pending = false;
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spin_unlock(&crtc->dev->event_lock);
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if (pending)
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drm_crtc_vblank_put(crtc);
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/* Wake up omap_atomic_complete. */
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wake_up(&omap_crtc->pending_wait);
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DBG("%s: apply done", omap_crtc->name);
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}
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static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
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{
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struct omap_drm_private *priv = crtc->dev->dev_private;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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struct omap_overlay_manager_info info;
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memset(&info, 0, sizeof(info));
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info.default_color = 0x000000;
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info.trans_enabled = false;
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info.partial_alpha_enabled = false;
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info.cpr_enable = false;
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priv->dispc_ops->mgr_setup(omap_crtc->channel, &info);
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}
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/* -----------------------------------------------------------------------------
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* CRTC Functions
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*/
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static void omap_crtc_destroy(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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DBG("%s", omap_crtc->name);
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drm_crtc_cleanup(crtc);
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kfree(omap_crtc);
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}
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static void omap_crtc_arm_event(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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WARN_ON(omap_crtc->pending);
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omap_crtc->pending = true;
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if (crtc->state->event) {
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omap_crtc->event = crtc->state->event;
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crtc->state->event = NULL;
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}
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}
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static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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int ret;
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DBG("%s", omap_crtc->name);
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spin_lock_irq(&crtc->dev->event_lock);
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drm_crtc_vblank_on(crtc);
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ret = drm_crtc_vblank_get(crtc);
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WARN_ON(ret != 0);
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omap_crtc_arm_event(crtc);
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spin_unlock_irq(&crtc->dev->event_lock);
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}
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static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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DBG("%s", omap_crtc->name);
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spin_lock_irq(&crtc->dev->event_lock);
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if (crtc->state->event) {
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drm_crtc_send_vblank_event(crtc, crtc->state->event);
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crtc->state->event = NULL;
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}
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spin_unlock_irq(&crtc->dev->event_lock);
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drm_crtc_vblank_off(crtc);
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}
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static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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struct omap_drm_private *priv = crtc->dev->dev_private;
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const u32 flags_mask = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_DE_LOW |
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DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
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DISPLAY_FLAGS_SYNC_POSEDGE | DISPLAY_FLAGS_SYNC_NEGEDGE;
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unsigned int i;
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DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
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omap_crtc->name, mode->base.id, mode->name,
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mode->vrefresh, mode->clock,
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mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
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mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
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mode->type, mode->flags);
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drm_display_mode_to_videomode(mode, &omap_crtc->vm);
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/*
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* HACK: This fixes the vm flags.
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* struct drm_display_mode does not contain the VSYNC/HSYNC/DE flags
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* and they get lost when converting back and forth between
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* struct drm_display_mode and struct videomode. The hack below
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* goes and fetches the missing flags from the panel drivers.
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*
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* Correct solution would be to use DRM's bus-flags, but that's not
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* easily possible before the omapdrm's panel/encoder driver model
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* has been changed to the DRM model.
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*/
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for (i = 0; i < priv->num_encoders; ++i) {
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struct drm_encoder *encoder = priv->encoders[i];
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if (encoder->crtc == crtc) {
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struct omap_dss_device *dssdev;
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dssdev = omap_encoder_get_dssdev(encoder);
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if (dssdev) {
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struct videomode vm = {0};
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dssdev->driver->get_timings(dssdev, &vm);
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omap_crtc->vm.flags |= vm.flags & flags_mask;
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}
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break;
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}
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}
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}
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static int omap_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct drm_plane_state *pri_state;
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if (state->color_mgmt_changed && state->gamma_lut) {
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uint length = state->gamma_lut->length /
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sizeof(struct drm_color_lut);
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if (length < 2)
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return -EINVAL;
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}
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pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary);
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if (pri_state) {
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struct omap_crtc_state *omap_crtc_state =
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to_omap_crtc_state(state);
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/* Mirror new values for zpos and rotation in omap_crtc_state */
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omap_crtc_state->zpos = pri_state->zpos;
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omap_crtc_state->rotation = pri_state->rotation;
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}
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return 0;
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}
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static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
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struct drm_crtc_state *old_crtc_state)
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{
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}
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static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_crtc_state *old_crtc_state)
|
|
{
|
|
struct omap_drm_private *priv = crtc->dev->dev_private;
|
|
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
|
|
int ret;
|
|
|
|
if (crtc->state->color_mgmt_changed) {
|
|
struct drm_color_lut *lut = NULL;
|
|
uint length = 0;
|
|
|
|
if (crtc->state->gamma_lut) {
|
|
lut = (struct drm_color_lut *)
|
|
crtc->state->gamma_lut->data;
|
|
length = crtc->state->gamma_lut->length /
|
|
sizeof(*lut);
|
|
}
|
|
priv->dispc_ops->mgr_set_gamma(omap_crtc->channel, lut, length);
|
|
}
|
|
|
|
omap_crtc_write_crtc_properties(crtc);
|
|
|
|
/* Only flush the CRTC if it is currently enabled. */
|
|
if (!omap_crtc->enabled)
|
|
return;
|
|
|
|
DBG("%s: GO", omap_crtc->name);
|
|
|
|
ret = drm_crtc_vblank_get(crtc);
|
|
WARN_ON(ret != 0);
|
|
|
|
spin_lock_irq(&crtc->dev->event_lock);
|
|
priv->dispc_ops->mgr_go(omap_crtc->channel);
|
|
omap_crtc_arm_event(crtc);
|
|
spin_unlock_irq(&crtc->dev->event_lock);
|
|
}
|
|
|
|
static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *state,
|
|
struct drm_property *property,
|
|
uint64_t val)
|
|
{
|
|
struct omap_drm_private *priv = crtc->dev->dev_private;
|
|
struct drm_plane_state *plane_state;
|
|
|
|
/*
|
|
* Delegate property set to the primary plane. Get the plane state and
|
|
* set the property directly, the shadow copy will be assigned in the
|
|
* omap_crtc_atomic_check callback. This way updates to plane state will
|
|
* always be mirrored in the crtc state correctly.
|
|
*/
|
|
plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
|
|
if (IS_ERR(plane_state))
|
|
return PTR_ERR(plane_state);
|
|
|
|
if (property == crtc->primary->rotation_property)
|
|
plane_state->rotation = val;
|
|
else if (property == priv->zorder_prop)
|
|
plane_state->zpos = val;
|
|
else
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
|
|
const struct drm_crtc_state *state,
|
|
struct drm_property *property,
|
|
uint64_t *val)
|
|
{
|
|
struct omap_drm_private *priv = crtc->dev->dev_private;
|
|
struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
|
|
|
|
if (property == crtc->primary->rotation_property)
|
|
*val = omap_state->rotation;
|
|
else if (property == priv->zorder_prop)
|
|
*val = omap_state->zpos;
|
|
else
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap_crtc_reset(struct drm_crtc *crtc)
|
|
{
|
|
if (crtc->state)
|
|
__drm_atomic_helper_crtc_destroy_state(crtc->state);
|
|
|
|
kfree(crtc->state);
|
|
crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL);
|
|
|
|
if (crtc->state)
|
|
crtc->state->crtc = crtc;
|
|
}
|
|
|
|
static struct drm_crtc_state *
|
|
omap_crtc_duplicate_state(struct drm_crtc *crtc)
|
|
{
|
|
struct omap_crtc_state *state, *current_state;
|
|
|
|
if (WARN_ON(!crtc->state))
|
|
return NULL;
|
|
|
|
current_state = to_omap_crtc_state(crtc->state);
|
|
|
|
state = kmalloc(sizeof(*state), GFP_KERNEL);
|
|
if (!state)
|
|
return NULL;
|
|
|
|
__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
|
|
|
|
state->zpos = current_state->zpos;
|
|
state->rotation = current_state->rotation;
|
|
|
|
return &state->base;
|
|
}
|
|
|
|
static const struct drm_crtc_funcs omap_crtc_funcs = {
|
|
.reset = omap_crtc_reset,
|
|
.set_config = drm_atomic_helper_set_config,
|
|
.destroy = omap_crtc_destroy,
|
|
.page_flip = drm_atomic_helper_page_flip,
|
|
.gamma_set = drm_atomic_helper_legacy_gamma_set,
|
|
.atomic_duplicate_state = omap_crtc_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
|
|
.atomic_set_property = omap_crtc_atomic_set_property,
|
|
.atomic_get_property = omap_crtc_atomic_get_property,
|
|
.enable_vblank = omap_irq_enable_vblank,
|
|
.disable_vblank = omap_irq_disable_vblank,
|
|
};
|
|
|
|
static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
|
|
.mode_set_nofb = omap_crtc_mode_set_nofb,
|
|
.atomic_check = omap_crtc_atomic_check,
|
|
.atomic_begin = omap_crtc_atomic_begin,
|
|
.atomic_flush = omap_crtc_atomic_flush,
|
|
.atomic_enable = omap_crtc_atomic_enable,
|
|
.atomic_disable = omap_crtc_atomic_disable,
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Init and Cleanup
|
|
*/
|
|
|
|
static const char *channel_names[] = {
|
|
[OMAP_DSS_CHANNEL_LCD] = "lcd",
|
|
[OMAP_DSS_CHANNEL_DIGIT] = "tv",
|
|
[OMAP_DSS_CHANNEL_LCD2] = "lcd2",
|
|
[OMAP_DSS_CHANNEL_LCD3] = "lcd3",
|
|
};
|
|
|
|
void omap_crtc_pre_init(void)
|
|
{
|
|
memset(omap_crtcs, 0, sizeof(omap_crtcs));
|
|
|
|
dss_install_mgr_ops(&mgr_ops);
|
|
}
|
|
|
|
void omap_crtc_pre_uninit(void)
|
|
{
|
|
dss_uninstall_mgr_ops();
|
|
}
|
|
|
|
/* initialize crtc */
|
|
struct drm_crtc *omap_crtc_init(struct drm_device *dev,
|
|
struct drm_plane *plane, struct omap_dss_device *dssdev)
|
|
{
|
|
struct omap_drm_private *priv = dev->dev_private;
|
|
struct drm_crtc *crtc = NULL;
|
|
struct omap_crtc *omap_crtc;
|
|
enum omap_channel channel;
|
|
struct omap_dss_device *out;
|
|
int ret;
|
|
|
|
out = omapdss_find_output_from_display(dssdev);
|
|
channel = out->dispc_channel;
|
|
omap_dss_put_device(out);
|
|
|
|
DBG("%s", channel_names[channel]);
|
|
|
|
/* Multiple displays on same channel is not allowed */
|
|
if (WARN_ON(omap_crtcs[channel] != NULL))
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
|
|
if (!omap_crtc)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
crtc = &omap_crtc->base;
|
|
|
|
init_waitqueue_head(&omap_crtc->pending_wait);
|
|
|
|
omap_crtc->channel = channel;
|
|
omap_crtc->name = channel_names[channel];
|
|
|
|
ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
|
|
&omap_crtc_funcs, NULL);
|
|
if (ret < 0) {
|
|
dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
|
|
__func__, dssdev->name);
|
|
kfree(omap_crtc);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
|
|
|
|
/* The dispc API adapts to what ever size, but the HW supports
|
|
* 256 element gamma table for LCDs and 1024 element table for
|
|
* OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
|
|
* tables so lets use that. Size of HW gamma table can be
|
|
* extracted with dispc_mgr_gamma_size(). If it returns 0
|
|
* gamma table is not supprted.
|
|
*/
|
|
if (priv->dispc_ops->mgr_gamma_size(channel)) {
|
|
uint gamma_lut_size = 256;
|
|
|
|
drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
|
|
drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
|
|
}
|
|
|
|
omap_plane_install_properties(crtc->primary, &crtc->base);
|
|
|
|
omap_crtcs[channel] = omap_crtc;
|
|
|
|
return crtc;
|
|
}
|