![Tomi Valkeinen](/assets/img/avatar_default.png)
Use dev_err_ratelimited() when an OCP error happens, to slightly easen the flood. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
296 lines
7.7 KiB
C
296 lines
7.7 KiB
C
/*
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* drivers/gpu/drm/omapdrm/omap_irq.c
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*
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* Copyright (C) 2012 Texas Instruments
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* Author: Rob Clark <rob.clark@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "omap_drv.h"
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struct omap_irq_wait {
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struct list_head node;
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wait_queue_head_t wq;
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uint32_t irqmask;
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int count;
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};
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/* call with wait_lock and dispc runtime held */
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static void omap_irq_update(struct drm_device *dev)
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{
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struct omap_drm_private *priv = dev->dev_private;
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struct omap_irq_wait *wait;
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uint32_t irqmask = priv->irq_mask;
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assert_spin_locked(&priv->wait_lock);
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list_for_each_entry(wait, &priv->wait_list, node)
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irqmask |= wait->irqmask;
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DBG("irqmask=%08x", irqmask);
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priv->dispc_ops->write_irqenable(irqmask);
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}
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static void omap_irq_wait_handler(struct omap_irq_wait *wait)
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{
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wait->count--;
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wake_up(&wait->wq);
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}
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struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev,
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uint32_t irqmask, int count)
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{
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struct omap_drm_private *priv = dev->dev_private;
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struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL);
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unsigned long flags;
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init_waitqueue_head(&wait->wq);
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wait->irqmask = irqmask;
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wait->count = count;
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spin_lock_irqsave(&priv->wait_lock, flags);
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list_add(&wait->node, &priv->wait_list);
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omap_irq_update(dev);
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spin_unlock_irqrestore(&priv->wait_lock, flags);
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return wait;
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}
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int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait,
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unsigned long timeout)
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{
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struct omap_drm_private *priv = dev->dev_private;
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unsigned long flags;
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int ret;
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ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout);
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spin_lock_irqsave(&priv->wait_lock, flags);
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list_del(&wait->node);
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omap_irq_update(dev);
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spin_unlock_irqrestore(&priv->wait_lock, flags);
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kfree(wait);
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return ret == 0 ? -1 : 0;
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}
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/**
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* enable_vblank - enable vblank interrupt events
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* @dev: DRM device
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* @pipe: which irq to enable
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*
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* Enable vblank interrupts for @crtc. If the device doesn't have
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* a hardware vblank counter, this routine should be a no-op, since
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* interrupts will have to stay on to keep the count accurate.
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*
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* RETURNS
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* Zero on success, appropriate errno if the given @crtc's vblank
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* interrupt cannot be enabled.
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*/
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int omap_irq_enable_vblank(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct omap_drm_private *priv = dev->dev_private;
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unsigned long flags;
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enum omap_channel channel = omap_crtc_channel(crtc);
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DBG("dev=%p, crtc=%u", dev, channel);
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spin_lock_irqsave(&priv->wait_lock, flags);
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priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(channel);
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omap_irq_update(dev);
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spin_unlock_irqrestore(&priv->wait_lock, flags);
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return 0;
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}
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/**
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* disable_vblank - disable vblank interrupt events
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* @dev: DRM device
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* @pipe: which irq to enable
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*
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* Disable vblank interrupts for @crtc. If the device doesn't have
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* a hardware vblank counter, this routine should be a no-op, since
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* interrupts will have to stay on to keep the count accurate.
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*/
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void omap_irq_disable_vblank(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct omap_drm_private *priv = dev->dev_private;
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unsigned long flags;
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enum omap_channel channel = omap_crtc_channel(crtc);
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DBG("dev=%p, crtc=%u", dev, channel);
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spin_lock_irqsave(&priv->wait_lock, flags);
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priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(channel);
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omap_irq_update(dev);
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spin_unlock_irqrestore(&priv->wait_lock, flags);
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}
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static void omap_irq_fifo_underflow(struct omap_drm_private *priv,
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u32 irqstatus)
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{
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static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL,
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DEFAULT_RATELIMIT_BURST);
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static const struct {
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const char *name;
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u32 mask;
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} sources[] = {
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{ "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW },
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{ "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW },
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{ "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW },
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{ "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW },
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};
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const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW
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| DISPC_IRQ_VID1_FIFO_UNDERFLOW
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| DISPC_IRQ_VID2_FIFO_UNDERFLOW
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| DISPC_IRQ_VID3_FIFO_UNDERFLOW;
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unsigned int i;
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spin_lock(&priv->wait_lock);
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irqstatus &= priv->irq_mask & mask;
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spin_unlock(&priv->wait_lock);
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if (!irqstatus)
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return;
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if (!__ratelimit(&_rs))
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return;
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DRM_ERROR("FIFO underflow on ");
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for (i = 0; i < ARRAY_SIZE(sources); ++i) {
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if (sources[i].mask & irqstatus)
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pr_cont("%s ", sources[i].name);
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}
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pr_cont("(0x%08x)\n", irqstatus);
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}
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static void omap_irq_ocp_error_handler(struct drm_device *dev,
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u32 irqstatus)
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{
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if (!(irqstatus & DISPC_IRQ_OCP_ERR))
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return;
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dev_err_ratelimited(dev->dev, "OCP error\n");
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}
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static irqreturn_t omap_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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struct omap_drm_private *priv = dev->dev_private;
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struct omap_irq_wait *wait, *n;
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unsigned long flags;
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unsigned int id;
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u32 irqstatus;
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irqstatus = priv->dispc_ops->read_irqstatus();
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priv->dispc_ops->clear_irqstatus(irqstatus);
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priv->dispc_ops->read_irqstatus(); /* flush posted write */
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VERB("irqs: %08x", irqstatus);
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for (id = 0; id < priv->num_crtcs; id++) {
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struct drm_crtc *crtc = priv->crtcs[id];
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enum omap_channel channel = omap_crtc_channel(crtc);
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if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(channel)) {
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drm_handle_vblank(dev, id);
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omap_crtc_vblank_irq(crtc);
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}
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if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(channel))
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omap_crtc_error_irq(crtc, irqstatus);
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}
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omap_irq_ocp_error_handler(dev, irqstatus);
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omap_irq_fifo_underflow(priv, irqstatus);
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spin_lock_irqsave(&priv->wait_lock, flags);
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list_for_each_entry_safe(wait, n, &priv->wait_list, node) {
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if (wait->irqmask & irqstatus)
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omap_irq_wait_handler(wait);
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}
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spin_unlock_irqrestore(&priv->wait_lock, flags);
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return IRQ_HANDLED;
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}
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static const u32 omap_underflow_irqs[] = {
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[OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW,
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[OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW,
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[OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW,
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[OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW,
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};
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/*
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* We need a special version, instead of just using drm_irq_install(),
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* because we need to register the irq via omapdss. Once omapdss and
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* omapdrm are merged together we can assign the dispc hwmod data to
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* ourselves and drop these and just use drm_irq_{install,uninstall}()
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*/
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int omap_drm_irq_install(struct drm_device *dev)
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{
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struct omap_drm_private *priv = dev->dev_private;
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unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs();
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unsigned int max_planes;
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unsigned int i;
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int ret;
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spin_lock_init(&priv->wait_lock);
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INIT_LIST_HEAD(&priv->wait_list);
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priv->irq_mask = DISPC_IRQ_OCP_ERR;
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max_planes = min(ARRAY_SIZE(priv->planes),
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ARRAY_SIZE(omap_underflow_irqs));
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for (i = 0; i < max_planes; ++i) {
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if (priv->planes[i])
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priv->irq_mask |= omap_underflow_irqs[i];
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}
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for (i = 0; i < num_mgrs; ++i)
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priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(i);
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priv->dispc_ops->runtime_get();
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priv->dispc_ops->clear_irqstatus(0xffffffff);
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priv->dispc_ops->runtime_put();
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ret = priv->dispc_ops->request_irq(omap_irq_handler, dev);
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if (ret < 0)
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return ret;
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dev->irq_enabled = true;
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return 0;
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}
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void omap_drm_irq_uninstall(struct drm_device *dev)
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{
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struct omap_drm_private *priv = dev->dev_private;
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if (!dev->irq_enabled)
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return;
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dev->irq_enabled = false;
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priv->dispc_ops->free_irq(dev);
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}
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