f81309067f
The existing memory barrier macro causes a significant amount of code to be inserted inline at every call site. For example, in gpio_set_irq_type(), we have this for mb(): c0344c08: f57ff04e dsb st c0344c0c: e59f8190 ldr r8, [pc, #400] ; c0344da4 <gpio_set_irq_type+0x230> c0344c10: e3590004 cmp r9, #4 c0344c14: e5983014 ldr r3, [r8, #20] c0344c18: 0a000054 beq c0344d70 <gpio_set_irq_type+0x1fc> c0344c1c: e3530000 cmp r3, #0 c0344c20: 0a000004 beq c0344c38 <gpio_set_irq_type+0xc4> c0344c24: e50b2030 str r2, [fp, #-48] ; 0xffffffd0 c0344c28: e50bc034 str ip, [fp, #-52] ; 0xffffffcc c0344c2c: e12fff33 blx r3 c0344c30: e51bc034 ldr ip, [fp, #-52] ; 0xffffffcc c0344c34: e51b2030 ldr r2, [fp, #-48] ; 0xffffffd0 c0344c38: e5963004 ldr r3, [r6, #4] Moving the outer_cache_sync() call out of line reduces the impact of the barrier: c0344968: f57ff04e dsb st c034496c: e35a0004 cmp sl, #4 c0344970: e50b2030 str r2, [fp, #-48] ; 0xffffffd0 c0344974: 0a000044 beq c0344a8c <gpio_set_irq_type+0x1b8> c0344978: ebf363dd bl c001d8f4 <arm_heavy_mb> c034497c: e5953004 ldr r3, [r5, #4] This should reduce the cache footprint of this code. Overall, this results in a reduction of around 20K in the kernel size: text data bss dec hex filename 10773970 667392 10369656 21811018 14ccf4a ../build/imx6/vmlinux-old 10754219 667392 10369656 21791267 14c8223 ../build/imx6/vmlinux-new Another advantage to this approach is that we can finally resolve the issue of SoCs which have their own memory barrier requirements within multiplatform kernels (such as OMAP.) Here, the bus interconnects need additional handling to ensure that writes become visible in the correct order (eg, between dma_map() operations, writes to DMA coherent memory, and MMIO accesses.) Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
133 lines
3.8 KiB
C
133 lines
3.8 KiB
C
/*
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* arch/arm/include/asm/outercache.h
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*
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* Copyright (C) 2010 ARM Ltd.
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* Written by Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_OUTERCACHE_H
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#define __ASM_OUTERCACHE_H
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#include <linux/types.h>
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struct l2x0_regs;
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struct outer_cache_fns {
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void (*inv_range)(unsigned long, unsigned long);
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void (*clean_range)(unsigned long, unsigned long);
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void (*flush_range)(unsigned long, unsigned long);
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void (*flush_all)(void);
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void (*disable)(void);
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#ifdef CONFIG_OUTER_CACHE_SYNC
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void (*sync)(void);
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#endif
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void (*resume)(void);
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/* This is an ARM L2C thing */
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void (*write_sec)(unsigned long, unsigned);
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void (*configure)(const struct l2x0_regs *);
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};
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extern struct outer_cache_fns outer_cache;
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#ifdef CONFIG_OUTER_CACHE
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/**
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* outer_inv_range - invalidate range of outer cache lines
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* @start: starting physical address, inclusive
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* @end: end physical address, exclusive
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*/
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static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
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{
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if (outer_cache.inv_range)
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outer_cache.inv_range(start, end);
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}
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/**
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* outer_clean_range - clean dirty outer cache lines
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* @start: starting physical address, inclusive
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* @end: end physical address, exclusive
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*/
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static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
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{
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if (outer_cache.clean_range)
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outer_cache.clean_range(start, end);
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}
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/**
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* outer_flush_range - clean and invalidate outer cache lines
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* @start: starting physical address, inclusive
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* @end: end physical address, exclusive
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*/
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static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
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{
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if (outer_cache.flush_range)
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outer_cache.flush_range(start, end);
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}
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/**
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* outer_flush_all - clean and invalidate all cache lines in the outer cache
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*
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* Note: depending on implementation, this may not be atomic - it must
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* only be called with interrupts disabled and no other active outer
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* cache masters.
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*
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* It is intended that this function is only used by implementations
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* needing to override the outer_cache.disable() method due to security.
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* (Some implementations perform this as a clean followed by an invalidate.)
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*/
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static inline void outer_flush_all(void)
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{
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if (outer_cache.flush_all)
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outer_cache.flush_all();
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}
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/**
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* outer_disable - clean, invalidate and disable the outer cache
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*
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* Disable the outer cache, ensuring that any data contained in the outer
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* cache is pushed out to lower levels of system memory. The note and
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* conditions above concerning outer_flush_all() applies here.
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*/
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extern void outer_disable(void);
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/**
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* outer_resume - restore the cache configuration and re-enable outer cache
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*
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* Restore any configuration that the cache had when previously enabled,
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* and re-enable the outer cache.
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*/
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static inline void outer_resume(void)
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{
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if (outer_cache.resume)
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outer_cache.resume();
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}
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#else
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static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
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{ }
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static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
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{ }
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static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
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{ }
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static inline void outer_flush_all(void) { }
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static inline void outer_disable(void) { }
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static inline void outer_resume(void) { }
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#endif
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#endif /* __ASM_OUTERCACHE_H */
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