1fa98174ba
This is necessary to set the dongle type on the nsc driver in order to get it to work correctly. Thinkpads all appear to use dongle type 9. This patch defaults nsc devices with an IBM PnP descriptor to use type 9. Signed-off-by: Matthew Garrett <mjg59@srcf.ucam.org> Signed-off-by: Ben Collins <ben.collins@canonical.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
284 lines
9.1 KiB
C
284 lines
9.1 KiB
C
/*********************************************************************
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*
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* Filename: nsc-ircc.h
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* Version:
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* Description:
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* Status: Experimental.
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* Author: Dag Brattli <dagb@cs.uit.no>
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* Created at: Fri Nov 13 14:37:40 1998
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* Modified at: Sun Jan 23 17:47:00 2000
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* Modified by: Dag Brattli <dagb@cs.uit.no>
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*
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* Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
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* Copyright (c) 1998 Lichen Wang, <lwang@actisys.com>
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* Copyright (c) 1998 Actisys Corp., www.actisys.com
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* Neither Dag Brattli nor University of Tromsø admit liability nor
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* provide warranty for any of this software. This material is
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* provided "AS-IS" and at no charge.
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*
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********************************************************************/
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#ifndef NSC_IRCC_H
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#define NSC_IRCC_H
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#include <linux/time.h>
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#include <linux/spinlock.h>
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#include <linux/pm.h>
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#include <linux/types.h>
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#include <asm/io.h>
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/* Features for chips (set in driver_data) */
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#define NSC_FORCE_DONGLE_TYPE9 0x00000001
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/* DMA modes needed */
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#define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */
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#define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */
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/* Config registers for the '108 */
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#define CFG_108_BAIC 0x00
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#define CFG_108_CSRT 0x01
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#define CFG_108_MCTL 0x02
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/* Config registers for the '338 */
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#define CFG_338_FER 0x00
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#define CFG_338_FAR 0x01
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#define CFG_338_PTR 0x02
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#define CFG_338_PNP0 0x1b
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#define CFG_338_PNP1 0x1c
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#define CFG_338_PNP3 0x4f
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/* Config registers for the '39x (in the logical device bank) */
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#define CFG_39X_LDN 0x07 /* Logical device number (Super I/O bank) */
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#define CFG_39X_SIOCF1 0x21 /* SuperI/O Config */
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#define CFG_39X_ACT 0x30 /* Device activation */
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#define CFG_39X_BASEH 0x60 /* Device base address (high bits) */
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#define CFG_39X_BASEL 0x61 /* Device base address (low bits) */
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#define CFG_39X_IRQNUM 0x70 /* Interrupt number & wake up enable */
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#define CFG_39X_IRQSEL 0x71 /* Interrupt select (edge/level + polarity) */
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#define CFG_39X_DMA0 0x74 /* DMA 0 configuration */
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#define CFG_39X_DMA1 0x75 /* DMA 1 configuration */
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#define CFG_39X_SPC 0xF0 /* Serial port configuration register */
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/* Flags for configuration register CRF0 */
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#define APEDCRC 0x02
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#define ENBNKSEL 0x01
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/* Set 0 */
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#define TXD 0x00 /* Transmit data port */
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#define RXD 0x00 /* Receive data port */
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/* Register 1 */
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#define IER 0x01 /* Interrupt Enable Register*/
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#define IER_RXHDL_IE 0x01 /* Receiver high data level interrupt */
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#define IER_TXLDL_IE 0x02 /* Transeiver low data level interrupt */
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#define IER_LS_IE 0x04//* Link Status Interrupt */
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#define IER_ETXURI 0x04 /* Tx underrun */
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#define IER_DMA_IE 0x10 /* DMA finished interrupt */
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#define IER_TXEMP_IE 0x20
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#define IER_SFIF_IE 0x40 /* Frame status FIFO intr */
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#define IER_TMR_IE 0x80 /* Timer event */
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#define FCR 0x02 /* (write only) */
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#define FCR_FIFO_EN 0x01 /* Enable FIFO's */
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#define FCR_RXSR 0x02 /* Rx FIFO soft reset */
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#define FCR_TXSR 0x04 /* Tx FIFO soft reset */
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#define FCR_RXTH 0x40 /* Rx FIFO threshold (set to 16) */
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#define FCR_TXTH 0x20 /* Tx FIFO threshold (set to 17) */
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#define EIR 0x02 /* (read only) */
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#define EIR_RXHDL_EV 0x01
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#define EIR_TXLDL_EV 0x02
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#define EIR_LS_EV 0x04
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#define EIR_DMA_EV 0x10
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#define EIR_TXEMP_EV 0x20
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#define EIR_SFIF_EV 0x40
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#define EIR_TMR_EV 0x80
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#define LCR 0x03 /* Link control register */
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#define LCR_WLS_8 0x03 /* 8 bits */
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#define BSR 0x03 /* Bank select register */
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#define BSR_BKSE 0x80
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#define BANK0 LCR_WLS_8 /* Must make sure that we set 8N1 */
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#define BANK1 0x80
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#define BANK2 0xe0
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#define BANK3 0xe4
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#define BANK4 0xe8
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#define BANK5 0xec
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#define BANK6 0xf0
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#define BANK7 0xf4
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#define MCR 0x04 /* Mode Control Register */
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#define MCR_MODE_MASK ~(0xd0)
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#define MCR_UART 0x00
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#define MCR_RESERVED 0x20
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#define MCR_SHARP_IR 0x40
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#define MCR_SIR 0x60
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#define MCR_MIR 0x80
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#define MCR_FIR 0xa0
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#define MCR_CEIR 0xb0
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#define MCR_IR_PLS 0x10
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#define MCR_DMA_EN 0x04
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#define MCR_EN_IRQ 0x08
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#define MCR_TX_DFR 0x08
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#define LSR 0x05 /* Link status register */
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#define LSR_RXDA 0x01 /* Receiver data available */
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#define LSR_TXRDY 0x20 /* Transmitter ready */
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#define LSR_TXEMP 0x40 /* Transmitter empty */
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#define ASCR 0x07 /* Auxillary Status and Control Register */
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#define ASCR_RXF_TOUT 0x01 /* Rx FIFO timeout */
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#define ASCR_FEND_INF 0x02 /* Frame end bytes in rx FIFO */
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#define ASCR_S_EOT 0x04 /* Set end of transmission */
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#define ASCT_RXBSY 0x20 /* Rx busy */
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#define ASCR_TXUR 0x40 /* Transeiver underrun */
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#define ASCR_CTE 0x80 /* Clear timer event */
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/* Bank 2 */
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#define BGDL 0x00 /* Baud Generator Divisor Port (Low Byte) */
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#define BGDH 0x01 /* Baud Generator Divisor Port (High Byte) */
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#define ECR1 0x02 /* Extended Control Register 1 */
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#define ECR1_EXT_SL 0x01 /* Extended Mode Select */
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#define ECR1_DMANF 0x02 /* DMA Fairness */
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#define ECR1_DMATH 0x04 /* DMA Threshold */
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#define ECR1_DMASWP 0x08 /* DMA Swap */
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#define EXCR2 0x04
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#define EXCR2_TFSIZ 0x01 /* Rx FIFO size = 32 */
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#define EXCR2_RFSIZ 0x04 /* Tx FIFO size = 32 */
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#define TXFLV 0x06 /* Tx FIFO level */
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#define RXFLV 0x07 /* Rx FIFO level */
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/* Bank 3 */
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#define MID 0x00
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/* Bank 4 */
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#define TMRL 0x00 /* Timer low byte */
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#define TMRH 0x01 /* Timer high byte */
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#define IRCR1 0x02 /* Infrared control register 1 */
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#define IRCR1_TMR_EN 0x01 /* Timer enable */
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#define TFRLL 0x04
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#define TFRLH 0x05
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#define RFRLL 0x06
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#define RFRLH 0x07
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/* Bank 5 */
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#define IRCR2 0x04 /* Infrared control register 2 */
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#define IRCR2_MDRS 0x04 /* MIR data rate select */
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#define IRCR2_FEND_MD 0x20 /* */
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#define FRM_ST 0x05 /* Frame status FIFO */
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#define FRM_ST_VLD 0x80 /* Frame status FIFO data valid */
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#define FRM_ST_ERR_MSK 0x5f
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#define FRM_ST_LOST_FR 0x40 /* Frame lost */
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#define FRM_ST_MAX_LEN 0x10 /* Max frame len exceeded */
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#define FRM_ST_PHY_ERR 0x08 /* Physical layer error */
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#define FRM_ST_BAD_CRC 0x04
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#define FRM_ST_OVR1 0x02 /* Rx FIFO overrun */
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#define FRM_ST_OVR2 0x01 /* Frame status FIFO overrun */
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#define RFLFL 0x06
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#define RFLFH 0x07
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/* Bank 6 */
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#define IR_CFG2 0x00
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#define IR_CFG2_DIS_CRC 0x02
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/* Bank 7 */
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#define IRM_CR 0x07 /* Infrared module control register */
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#define IRM_CR_IRX_MSL 0x40
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#define IRM_CR_AF_MNT 0x80 /* Automatic format */
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/* NSC chip information */
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struct nsc_chip {
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char *name; /* Name of chipset */
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int cfg[3]; /* Config registers */
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u_int8_t cid_index; /* Chip identification index reg */
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u_int8_t cid_value; /* Chip identification expected value */
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u_int8_t cid_mask; /* Chip identification revision mask */
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/* Functions for probing and initializing the specific chip */
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int (*probe)(struct nsc_chip *chip, chipio_t *info);
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int (*init)(struct nsc_chip *chip, chipio_t *info);
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};
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typedef struct nsc_chip nsc_chip_t;
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/* For storing entries in the status FIFO */
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struct st_fifo_entry {
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int status;
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int len;
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};
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#define MAX_TX_WINDOW 7
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#define MAX_RX_WINDOW 7
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struct st_fifo {
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struct st_fifo_entry entries[MAX_RX_WINDOW];
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int pending_bytes;
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int head;
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int tail;
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int len;
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};
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struct frame_cb {
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void *start; /* Start of frame in DMA mem */
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int len; /* Length of frame in DMA mem */
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};
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struct tx_fifo {
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struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */
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int ptr; /* Currently being sent */
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int len; /* Length of queue */
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int free; /* Next free slot */
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void *tail; /* Next free start in DMA mem */
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};
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/* Private data for each instance */
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struct nsc_ircc_cb {
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struct st_fifo st_fifo; /* Info about received frames */
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struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
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struct net_device *netdev; /* Yes! we are some kind of netdevice */
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struct net_device_stats stats;
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struct irlap_cb *irlap; /* The link layer we are binded to */
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struct qos_info qos; /* QoS capabilities for this device */
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chipio_t io; /* IrDA controller information */
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iobuff_t tx_buff; /* Transmit buffer */
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iobuff_t rx_buff; /* Receive buffer */
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dma_addr_t tx_buff_dma;
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dma_addr_t rx_buff_dma;
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__u8 ier; /* Interrupt enable register */
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struct timeval stamp;
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struct timeval now;
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spinlock_t lock; /* For serializing operations */
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__u32 new_speed;
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int index; /* Instance index */
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struct platform_device *pldev;
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};
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static inline void switch_bank(int iobase, int bank)
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{
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outb(bank, iobase+BSR);
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}
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#endif /* NSC_IRCC_H */
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