![Roland Stigge](/assets/img/avatar_default.png)
During a complex merge for v3.4, one line of the commit
c20b909be9
("ARM: LPC32xx: Ethernet support") was
reverted wrongly ("lpc-eth.0" -> "lpc-net.0") while the other conflicts were
merged correctly. This patch re-applies the clock name "lpc-eth.0".
Signed-off-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
1192 lines
32 KiB
C
1192 lines
32 KiB
C
/*
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* arch/arm/mach-lpc32xx/clock.c
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* LPC32xx clock management driver overview
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*
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* The LPC32XX contains a number of high level system clocks that can be
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* generated from different sources. These system clocks are used to
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* generate the CPU and bus rates and the individual peripheral clocks in
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* the system. When Linux is started by the boot loader, the system
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* clocks are already running. Stopping a system clock during normal
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* Linux operation should never be attempted, as peripherals that require
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* those clocks will quit working (ie, DRAM).
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*
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* The LPC32xx high level clock tree looks as follows. Clocks marked with
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* an asterisk are always on and cannot be disabled. Clocks marked with
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* an ampersand can only be disabled in CPU suspend mode. Clocks marked
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* with a caret are always on if it is the selected clock for the SYSCLK
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* source. The clock that isn't used for SYSCLK can be enabled and
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* disabled normally.
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* 32KHz oscillator*
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* / | \
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* RTC* PLL397^ TOUCH
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* /
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* Main oscillator^ /
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* | \ /
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* | SYSCLK&
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* | \
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* | \
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* USB_PLL HCLK_PLL&
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* | | |
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* USB host/device PCLK& |
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* | |
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* Peripherals
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*
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* The CPU and chip bus rates are derived from the HCLK PLL, which can
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* generate various clock rates up to 266MHz and beyond. The internal bus
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* rates (PCLK and HCLK) are generated from dividers based on the HCLK
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* PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
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* while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
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* level clocks are based on either HCLK or PCLK, but have their own
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* dividers as part of the IP itself. Because of this, the system clock
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* rates should not be changed.
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*
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* The HCLK PLL is clocked from SYSCLK, which can be derived from the
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* main oscillator or PLL397. PLL397 generates a rate that is 397 times
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* the 32KHz oscillator rate. The main oscillator runs at the selected
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* oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
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* is normally 13MHz, but depends on the selection of external crystals
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* or oscillators. If USB operation is required, the main oscillator must
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* be used in the system.
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*
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* Switching SYSCLK between sources during normal Linux operation is not
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* supported. SYSCLK is preset in the bootloader. Because of the
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* complexities of clock management during clock frequency changes,
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* there are some limitations to the clock driver explained below:
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* - The PLL397 and main oscillator can be enabled and disabled by the
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* clk_enable() and clk_disable() functions unless SYSCLK is based
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* on that clock. This allows the other oscillator that isn't driving
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* the HCLK PLL to be used as another system clock that can be routed
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* to an external pin.
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* - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
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* this driver.
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* - HCLK and PCLK rates cannot be changed as part of this driver.
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* - Most peripherals have their own dividers are part of the peripheral
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* block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
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* will also impact the individual peripheral rates.
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*/
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <linux/clkdev.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "clock.h"
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#include "common.h"
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static DEFINE_SPINLOCK(global_clkregs_lock);
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static int usb_pll_enable, usb_pll_valid;
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static struct clk clk_armpll;
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static struct clk clk_usbpll;
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/*
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* Post divider values for PLLs based on selected register value
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*/
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static const u32 pll_postdivs[4] = {1, 2, 4, 8};
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static unsigned long local_return_parent_rate(struct clk *clk)
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{
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/*
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* If a clock has a rate of 0, then it inherits it's parent
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* clock rate
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*/
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while (clk->rate == 0)
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clk = clk->parent;
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return clk->rate;
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}
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/* 32KHz clock has a fixed rate and is not stoppable */
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static struct clk osc_32KHz = {
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.rate = LPC32XX_CLOCK_OSC_FREQ,
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.get_rate = local_return_parent_rate,
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};
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static int local_pll397_enable(struct clk *clk, int enable)
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{
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u32 reg;
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
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if (enable == 0) {
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reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
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__raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
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} else {
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/* Enable PLL397 */
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reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
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__raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
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/* Wait for PLL397 lock */
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while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
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LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
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time_before(jiffies, timeout))
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cpu_relax();
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if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
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LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
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return -ENODEV;
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}
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return 0;
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}
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static int local_oscmain_enable(struct clk *clk, int enable)
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{
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u32 reg;
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
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if (enable == 0) {
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reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
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__raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
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} else {
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/* Enable main oscillator */
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reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
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__raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
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/* Wait for main oscillator to start */
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while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
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LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
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time_before(jiffies, timeout))
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cpu_relax();
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if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
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LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
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return -ENODEV;
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}
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return 0;
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}
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static struct clk osc_pll397 = {
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.parent = &osc_32KHz,
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.enable = local_pll397_enable,
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.rate = LPC32XX_CLOCK_OSC_FREQ * 397,
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.get_rate = local_return_parent_rate,
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};
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static struct clk osc_main = {
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.enable = local_oscmain_enable,
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.rate = LPC32XX_MAIN_OSC_FREQ,
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.get_rate = local_return_parent_rate,
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};
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static struct clk clk_sys;
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/*
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* Convert a PLL register value to a PLL output frequency
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*/
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u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
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{
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struct clk_pll_setup pllcfg;
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pllcfg.cco_bypass_b15 = 0;
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pllcfg.direct_output_b14 = 0;
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pllcfg.fdbk_div_ctrl_b13 = 0;
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if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
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pllcfg.cco_bypass_b15 = 1;
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if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
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pllcfg.direct_output_b14 = 1;
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if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
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pllcfg.fdbk_div_ctrl_b13 = 1;
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pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
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pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
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pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
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return clk_check_pll_setup(inputclk, &pllcfg);
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}
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/*
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* Setup the HCLK PLL with a PLL structure
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*/
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static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
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{
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u32 tv, tmp = 0;
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if (PllSetup->analog_on != 0)
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tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
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if (PllSetup->cco_bypass_b15 != 0)
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tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
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if (PllSetup->direct_output_b14 != 0)
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tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
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if (PllSetup->fdbk_div_ctrl_b13 != 0)
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tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
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tv = ffs(PllSetup->pll_p) - 1;
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if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
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return 0;
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tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
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tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
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tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
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return tmp;
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}
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/*
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* Update the ARM core PLL frequency rate variable from the actual PLL setting
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*/
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static void local_update_armpll_rate(void)
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{
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u32 clkin, pllreg;
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clkin = clk_armpll.parent->rate;
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pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
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clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
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}
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/*
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* Find a PLL configuration for the selected input frequency
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*/
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static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
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struct clk_pll_setup *pllsetup)
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{
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u32 ifreq, freqtol, m, n, p, fclkout;
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/* Determine frequency tolerance limits */
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freqtol = target_freq / 250;
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ifreq = pllin_freq;
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/* Is direct bypass mode possible? */
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if (abs(pllin_freq - target_freq) <= freqtol) {
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pllsetup->analog_on = 0;
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pllsetup->cco_bypass_b15 = 1;
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pllsetup->direct_output_b14 = 1;
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pllsetup->fdbk_div_ctrl_b13 = 1;
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pllsetup->pll_p = pll_postdivs[0];
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pllsetup->pll_n = 1;
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pllsetup->pll_m = 1;
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return clk_check_pll_setup(ifreq, pllsetup);
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} else if (target_freq <= ifreq) {
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pllsetup->analog_on = 0;
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pllsetup->cco_bypass_b15 = 1;
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pllsetup->direct_output_b14 = 0;
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pllsetup->fdbk_div_ctrl_b13 = 1;
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pllsetup->pll_n = 1;
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pllsetup->pll_m = 1;
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for (p = 0; p <= 3; p++) {
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pllsetup->pll_p = pll_postdivs[p];
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fclkout = clk_check_pll_setup(ifreq, pllsetup);
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if (abs(target_freq - fclkout) <= freqtol)
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return fclkout;
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}
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}
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/* Is direct mode possible? */
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pllsetup->analog_on = 1;
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pllsetup->cco_bypass_b15 = 0;
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pllsetup->direct_output_b14 = 1;
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pllsetup->fdbk_div_ctrl_b13 = 0;
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pllsetup->pll_p = pll_postdivs[0];
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for (m = 1; m <= 256; m++) {
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for (n = 1; n <= 4; n++) {
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/* Compute output frequency for this value */
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pllsetup->pll_n = n;
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pllsetup->pll_m = m;
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fclkout = clk_check_pll_setup(ifreq,
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pllsetup);
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if (abs(target_freq - fclkout) <=
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freqtol)
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return fclkout;
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}
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}
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/* Is integer mode possible? */
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pllsetup->analog_on = 1;
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pllsetup->cco_bypass_b15 = 0;
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pllsetup->direct_output_b14 = 0;
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pllsetup->fdbk_div_ctrl_b13 = 1;
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for (m = 1; m <= 256; m++) {
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for (n = 1; n <= 4; n++) {
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for (p = 0; p < 4; p++) {
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/* Compute output frequency */
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pllsetup->pll_p = pll_postdivs[p];
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pllsetup->pll_n = n;
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pllsetup->pll_m = m;
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fclkout = clk_check_pll_setup(
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ifreq, pllsetup);
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if (abs(target_freq - fclkout) <= freqtol)
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return fclkout;
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}
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}
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}
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/* Try non-integer mode */
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pllsetup->analog_on = 1;
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pllsetup->cco_bypass_b15 = 0;
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pllsetup->direct_output_b14 = 0;
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pllsetup->fdbk_div_ctrl_b13 = 0;
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for (m = 1; m <= 256; m++) {
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for (n = 1; n <= 4; n++) {
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for (p = 0; p < 4; p++) {
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/* Compute output frequency */
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pllsetup->pll_p = pll_postdivs[p];
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pllsetup->pll_n = n;
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pllsetup->pll_m = m;
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fclkout = clk_check_pll_setup(
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ifreq, pllsetup);
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if (abs(target_freq - fclkout) <= freqtol)
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return fclkout;
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}
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}
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}
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return 0;
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}
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static struct clk clk_armpll = {
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.parent = &clk_sys,
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.get_rate = local_return_parent_rate,
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};
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/*
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* Setup the USB PLL with a PLL structure
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*/
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static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
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{
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u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
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reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
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reg |= tmp;
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__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
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return clk_check_pll_setup(clk_usbpll.parent->rate,
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pHCLKPllSetup);
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}
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static int local_usbpll_enable(struct clk *clk, int enable)
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{
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u32 reg;
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int ret = 0;
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unsigned long timeout = jiffies + msecs_to_jiffies(20);
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reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
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__raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 |
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LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
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LPC32XX_CLKPWR_USB_CTRL);
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__raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1,
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LPC32XX_CLKPWR_USB_CTRL);
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if (enable && usb_pll_valid && usb_pll_enable) {
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ret = -ENODEV;
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/*
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* If the PLL rate has been previously set, then the rate
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* in the PLL register is valid and can be enabled here.
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* Otherwise, it needs to be enabled as part of setrate.
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*/
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/*
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* Gate clock into PLL
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*/
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reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
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__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
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/*
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* Enable PLL
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*/
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reg |= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP;
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__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
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/*
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* Wait for PLL to lock
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*/
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while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
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reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
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if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
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ret = 0;
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else
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udelay(10);
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}
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/*
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* Gate clock from PLL if PLL is locked
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*/
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if (ret == 0) {
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__raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2,
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LPC32XX_CLKPWR_USB_CTRL);
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} else {
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__raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
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LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
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LPC32XX_CLKPWR_USB_CTRL);
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}
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} else if ((enable == 0) && usb_pll_valid && usb_pll_enable) {
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usb_pll_valid = 0;
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usb_pll_enable = 0;
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}
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return ret;
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}
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static unsigned long local_usbpll_round_rate(struct clk *clk,
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unsigned long rate)
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{
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u32 clkin, usbdiv;
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struct clk_pll_setup pllsetup;
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/*
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* Unlike other clocks, this clock has a KHz input rate, so bump
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* it up to work with the PLL function
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*/
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rate = rate * 1000;
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clkin = clk->get_rate(clk);
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usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
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LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
|
|
clkin = clkin / usbdiv;
|
|
|
|
/* Try to find a good rate setup */
|
|
if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
|
|
return 0;
|
|
|
|
return clk_check_pll_setup(clkin, &pllsetup);
|
|
}
|
|
|
|
static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = -ENODEV;
|
|
u32 clkin, usbdiv;
|
|
struct clk_pll_setup pllsetup;
|
|
|
|
/*
|
|
* Unlike other clocks, this clock has a KHz input rate, so bump
|
|
* it up to work with the PLL function
|
|
*/
|
|
rate = rate * 1000;
|
|
|
|
clkin = clk->get_rate(clk->parent);
|
|
usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
|
|
LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
|
|
clkin = clkin / usbdiv;
|
|
|
|
/* Try to find a good rate setup */
|
|
if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Disable PLL clocks during PLL change
|
|
*/
|
|
local_usbpll_enable(clk, 0);
|
|
pllsetup.analog_on = 0;
|
|
local_clk_usbpll_setup(&pllsetup);
|
|
|
|
/*
|
|
* Start USB PLL and check PLL status
|
|
*/
|
|
|
|
usb_pll_valid = 1;
|
|
usb_pll_enable = 1;
|
|
|
|
ret = local_usbpll_enable(clk, 1);
|
|
if (ret >= 0)
|
|
clk->rate = clk_check_pll_setup(clkin, &pllsetup);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct clk clk_usbpll = {
|
|
.parent = &osc_main,
|
|
.set_rate = local_usbpll_set_rate,
|
|
.enable = local_usbpll_enable,
|
|
.rate = 48000, /* In KHz */
|
|
.get_rate = local_return_parent_rate,
|
|
.round_rate = local_usbpll_round_rate,
|
|
};
|
|
|
|
static u32 clk_get_hclk_div(void)
|
|
{
|
|
static const u32 hclkdivs[4] = {1, 2, 4, 4};
|
|
return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
|
|
__raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
|
|
}
|
|
|
|
static struct clk clk_hclk = {
|
|
.parent = &clk_armpll,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_pclk = {
|
|
.parent = &clk_armpll,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static int local_onoff_enable(struct clk *clk, int enable)
|
|
{
|
|
u32 tmp;
|
|
|
|
tmp = __raw_readl(clk->enable_reg);
|
|
|
|
if (enable == 0)
|
|
tmp &= ~clk->enable_mask;
|
|
else
|
|
tmp |= clk->enable_mask;
|
|
|
|
__raw_writel(tmp, clk->enable_reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Peripheral clock sources */
|
|
static struct clk clk_timer0 = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
|
|
.enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
static struct clk clk_timer1 = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
|
|
.enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
static struct clk clk_timer2 = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
|
|
.enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
static struct clk clk_timer3 = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
|
|
.enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
static struct clk clk_wdt = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
static struct clk clk_vfp9 = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
static struct clk clk_dma = {
|
|
.parent = &clk_hclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_uart3 = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_uart4 = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_uart5 = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_uart6 = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_i2c0 = {
|
|
.parent = &clk_hclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_i2c1 = {
|
|
.parent = &clk_hclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_i2c2 = {
|
|
.parent = &clk_pclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = io_p2v(LPC32XX_USB_BASE + 0xFF4),
|
|
.enable_mask = 0x4,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_ssp0 = {
|
|
.parent = &clk_hclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_ssp1 = {
|
|
.parent = &clk_hclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_kscan = {
|
|
.parent = &osc_32KHz,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_KEY_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_nand = {
|
|
.parent = &clk_hclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_i2s0 = {
|
|
.parent = &clk_hclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_i2s1 = {
|
|
.parent = &clk_hclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_net = {
|
|
.parent = &clk_hclk,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_MACCLK_CTRL,
|
|
.enable_mask = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
|
|
LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
|
|
LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_rtc = {
|
|
.parent = &osc_32KHz,
|
|
.rate = 1, /* 1 Hz */
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static struct clk clk_usbd = {
|
|
.parent = &clk_usbpll,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_USB_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static int tsc_onoff_enable(struct clk *clk, int enable)
|
|
{
|
|
u32 tmp;
|
|
|
|
/* Make sure 32KHz clock is the selected clock */
|
|
tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
|
|
tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
|
|
__raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
|
|
|
|
if (enable == 0)
|
|
__raw_writel(0, clk->enable_reg);
|
|
else
|
|
__raw_writel(clk->enable_mask, clk->enable_reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk clk_tsc = {
|
|
.parent = &osc_32KHz,
|
|
.enable = tsc_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static int adc_onoff_enable(struct clk *clk, int enable)
|
|
{
|
|
u32 tmp;
|
|
u32 divider;
|
|
|
|
/* Use PERIPH_CLOCK */
|
|
tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
|
|
tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
|
|
/*
|
|
* Set clock divider so that we have equal to or less than
|
|
* 4.5MHz clock at ADC
|
|
*/
|
|
divider = clk->get_rate(clk) / 4500000 + 1;
|
|
tmp |= divider;
|
|
__raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
|
|
|
|
/* synchronize rate of this clock w/ actual HW setting */
|
|
clk->rate = clk->get_rate(clk->parent) / divider;
|
|
|
|
if (enable == 0)
|
|
__raw_writel(0, clk->enable_reg);
|
|
else
|
|
__raw_writel(clk->enable_mask, clk->enable_reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk clk_adc = {
|
|
.parent = &clk_pclk,
|
|
.enable = adc_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
|
|
.get_rate = local_return_parent_rate,
|
|
};
|
|
|
|
static int mmc_onoff_enable(struct clk *clk, int enable)
|
|
{
|
|
u32 tmp;
|
|
|
|
tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
|
|
~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
|
|
|
|
/* If rate is 0, disable clock */
|
|
if (enable != 0)
|
|
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
|
|
|
|
__raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long mmc_get_rate(struct clk *clk)
|
|
{
|
|
u32 div, rate, oldclk;
|
|
|
|
/* The MMC clock must be on when accessing an MMC register */
|
|
oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
|
|
__raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
|
|
LPC32XX_CLKPWR_MS_CTRL);
|
|
div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
|
|
__raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
|
|
|
|
/* Get the parent clock rate */
|
|
rate = clk->parent->get_rate(clk->parent);
|
|
|
|
/* Get the MMC controller clock divider value */
|
|
div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
|
|
|
|
if (!div)
|
|
div = 1;
|
|
|
|
return rate / div;
|
|
}
|
|
|
|
static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
unsigned long div, prate;
|
|
|
|
/* Get the parent clock rate */
|
|
prate = clk->parent->get_rate(clk->parent);
|
|
|
|
if (rate >= prate)
|
|
return prate;
|
|
|
|
div = prate / rate;
|
|
if (div > 0xf)
|
|
div = 0xf;
|
|
|
|
return prate / div;
|
|
}
|
|
|
|
static int mmc_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
u32 oldclk, tmp;
|
|
unsigned long prate, div, crate = mmc_round_rate(clk, rate);
|
|
|
|
prate = clk->parent->get_rate(clk->parent);
|
|
|
|
div = prate / crate;
|
|
|
|
/* The MMC clock must be on when accessing an MMC register */
|
|
oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
|
|
__raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
|
|
LPC32XX_CLKPWR_MS_CTRL);
|
|
tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
|
|
~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
|
|
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
|
|
__raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
|
|
|
|
__raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk clk_mmc = {
|
|
.parent = &clk_armpll,
|
|
.set_rate = mmc_set_rate,
|
|
.get_rate = mmc_get_rate,
|
|
.round_rate = mmc_round_rate,
|
|
.enable = mmc_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_MS_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
|
|
};
|
|
|
|
static unsigned long clcd_get_rate(struct clk *clk)
|
|
{
|
|
u32 tmp, div, rate, oldclk;
|
|
|
|
/* The LCD clock must be on when accessing an LCD register */
|
|
oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
|
|
__raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
|
|
LPC32XX_CLKPWR_LCDCLK_CTRL);
|
|
tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
|
|
__raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
|
|
|
|
rate = clk->parent->get_rate(clk->parent);
|
|
|
|
/* Only supports internal clocking */
|
|
if (tmp & TIM2_BCD)
|
|
return rate;
|
|
|
|
div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
|
|
tmp = rate / (2 + div);
|
|
|
|
return tmp;
|
|
}
|
|
|
|
static int clcd_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
u32 tmp, prate, div, oldclk;
|
|
|
|
/* The LCD clock must be on when accessing an LCD register */
|
|
oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
|
|
__raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
|
|
LPC32XX_CLKPWR_LCDCLK_CTRL);
|
|
|
|
tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
|
|
prate = clk->parent->get_rate(clk->parent);
|
|
|
|
if (rate < prate) {
|
|
/* Find closest divider */
|
|
div = prate / rate;
|
|
if (div >= 2) {
|
|
div -= 2;
|
|
tmp &= ~TIM2_BCD;
|
|
}
|
|
|
|
tmp &= ~(0xF800001F);
|
|
tmp |= (div & 0x1F);
|
|
tmp |= (((div >> 5) & 0x1F) << 27);
|
|
}
|
|
|
|
__raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
|
|
__raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
u32 prate, div;
|
|
|
|
prate = clk->parent->get_rate(clk->parent);
|
|
|
|
if (rate >= prate)
|
|
rate = prate;
|
|
else {
|
|
div = prate / rate;
|
|
if (div > 0x3ff)
|
|
div = 0x3ff;
|
|
|
|
rate = prate / div;
|
|
}
|
|
|
|
return rate;
|
|
}
|
|
|
|
static struct clk clk_lcd = {
|
|
.parent = &clk_hclk,
|
|
.set_rate = clcd_set_rate,
|
|
.get_rate = clcd_get_rate,
|
|
.round_rate = clcd_round_rate,
|
|
.enable = local_onoff_enable,
|
|
.enable_reg = LPC32XX_CLKPWR_LCDCLK_CTRL,
|
|
.enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
|
|
};
|
|
|
|
static void local_clk_disable(struct clk *clk)
|
|
{
|
|
/* Don't attempt to disable clock if it has no users */
|
|
if (clk->usecount > 0) {
|
|
clk->usecount--;
|
|
|
|
/* Only disable clock when it has no more users */
|
|
if ((clk->usecount == 0) && (clk->enable))
|
|
clk->enable(clk, 0);
|
|
|
|
/* Check parent clocks, they may need to be disabled too */
|
|
if (clk->parent)
|
|
local_clk_disable(clk->parent);
|
|
}
|
|
}
|
|
|
|
static int local_clk_enable(struct clk *clk)
|
|
{
|
|
int ret = 0;
|
|
|
|
/* Enable parent clocks first and update use counts */
|
|
if (clk->parent)
|
|
ret = local_clk_enable(clk->parent);
|
|
|
|
if (!ret) {
|
|
/* Only enable clock if it's currently disabled */
|
|
if ((clk->usecount == 0) && (clk->enable))
|
|
ret = clk->enable(clk, 1);
|
|
|
|
if (!ret)
|
|
clk->usecount++;
|
|
else if (clk->parent)
|
|
local_clk_disable(clk->parent);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* clk_enable - inform the system when the clock source should be running.
|
|
*/
|
|
int clk_enable(struct clk *clk)
|
|
{
|
|
int ret;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&global_clkregs_lock, flags);
|
|
ret = local_clk_enable(clk);
|
|
spin_unlock_irqrestore(&global_clkregs_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(clk_enable);
|
|
|
|
/*
|
|
* clk_disable - inform the system when the clock source is no longer required
|
|
*/
|
|
void clk_disable(struct clk *clk)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&global_clkregs_lock, flags);
|
|
local_clk_disable(clk);
|
|
spin_unlock_irqrestore(&global_clkregs_lock, flags);
|
|
}
|
|
EXPORT_SYMBOL(clk_disable);
|
|
|
|
/*
|
|
* clk_get_rate - obtain the current clock rate (in Hz) for a clock source
|
|
*/
|
|
unsigned long clk_get_rate(struct clk *clk)
|
|
{
|
|
return clk->get_rate(clk);
|
|
}
|
|
EXPORT_SYMBOL(clk_get_rate);
|
|
|
|
/*
|
|
* clk_set_rate - set the clock rate for a clock source
|
|
*/
|
|
int clk_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = -EINVAL;
|
|
|
|
/*
|
|
* Most system clocks can only be enabled or disabled, with
|
|
* the actual rate set as part of the peripheral dividers
|
|
* instead of high level clock control
|
|
*/
|
|
if (clk->set_rate)
|
|
ret = clk->set_rate(clk, rate);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(clk_set_rate);
|
|
|
|
/*
|
|
* clk_round_rate - adjust a rate to the exact rate a clock can provide
|
|
*/
|
|
long clk_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
if (clk->round_rate)
|
|
rate = clk->round_rate(clk, rate);
|
|
else
|
|
rate = clk->get_rate(clk);
|
|
|
|
return rate;
|
|
}
|
|
EXPORT_SYMBOL(clk_round_rate);
|
|
|
|
/*
|
|
* clk_set_parent - set the parent clock source for this clock
|
|
*/
|
|
int clk_set_parent(struct clk *clk, struct clk *parent)
|
|
{
|
|
/* Clock re-parenting is not supported */
|
|
return -EINVAL;
|
|
}
|
|
EXPORT_SYMBOL(clk_set_parent);
|
|
|
|
/*
|
|
* clk_get_parent - get the parent clock source for this clock
|
|
*/
|
|
struct clk *clk_get_parent(struct clk *clk)
|
|
{
|
|
return clk->parent;
|
|
}
|
|
EXPORT_SYMBOL(clk_get_parent);
|
|
|
|
#define _REGISTER_CLOCK(d, n, c) \
|
|
{ \
|
|
.dev_id = (d), \
|
|
.con_id = (n), \
|
|
.clk = &(c), \
|
|
},
|
|
|
|
static struct clk_lookup lookups[] = {
|
|
_REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
|
|
_REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
|
|
_REGISTER_CLOCK(NULL, "osc_main", osc_main)
|
|
_REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
|
|
_REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
|
|
_REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
|
|
_REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
|
|
_REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
|
|
_REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
|
|
_REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
|
|
_REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
|
|
_REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
|
|
_REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
|
|
_REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
|
|
_REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
|
|
_REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
|
|
_REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
|
|
_REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
|
|
_REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
|
|
_REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
|
|
_REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
|
|
_REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
|
|
_REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
|
|
_REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
|
|
_REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
|
|
_REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
|
|
_REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
|
|
_REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
|
|
_REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
|
|
_REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
|
|
_REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
|
|
_REGISTER_CLOCK("lpc-eth.0", NULL, clk_net)
|
|
_REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
|
|
_REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
|
|
_REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
|
|
};
|
|
|
|
static int __init clk_init(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(lookups); i++)
|
|
clkdev_add(&lookups[i]);
|
|
|
|
/*
|
|
* Setup muxed SYSCLK for HCLK PLL base -this selects the
|
|
* parent clock used for the ARM PLL and is used to derive
|
|
* the many system clock rates in the device.
|
|
*/
|
|
if (clk_is_sysclk_mainosc() != 0)
|
|
clk_sys.parent = &osc_main;
|
|
else
|
|
clk_sys.parent = &osc_pll397;
|
|
|
|
clk_sys.rate = clk_sys.parent->rate;
|
|
|
|
/* Compute the current ARM PLL and USB PLL frequencies */
|
|
local_update_armpll_rate();
|
|
|
|
/* Compute HCLK and PCLK bus rates */
|
|
clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
|
|
clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
|
|
|
|
/*
|
|
* Enable system clocks - this step is somewhat formal, as the
|
|
* clocks are already running, but it does get the clock data
|
|
* inline with the actual system state. Never disable these
|
|
* clocks as they will only stop if the system is going to sleep.
|
|
* In that case, the chip/system power management functions will
|
|
* handle clock gating.
|
|
*/
|
|
if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
|
|
printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
|
|
|
|
/*
|
|
* Timers 0 and 1 were enabled and are being used by the high
|
|
* resolution tick function prior to this driver being initialized.
|
|
* Tag them now as used.
|
|
*/
|
|
if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
|
|
printk(KERN_ERR "Error enabling timer tick clocks\n");
|
|
|
|
return 0;
|
|
}
|
|
core_initcall(clk_init);
|
|
|