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With LPAE, TTBRx registers are 64-bit. The ASID is stored in TTBR0 rather than a separate Context ID register. This patch makes the necessary changes to handle context switching on LPAE. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
173 lines
4.2 KiB
C
173 lines
4.2 KiB
C
/*
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* linux/arch/arm/mm/context.c
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*
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* Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/percpu.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
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unsigned int cpu_last_asid = ASID_FIRST_VERSION;
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#ifdef CONFIG_SMP
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DEFINE_PER_CPU(struct mm_struct *, current_mm);
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#endif
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#ifdef CONFIG_ARM_LPAE
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#define cpu_set_asid(asid) { \
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unsigned long ttbl, ttbh; \
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asm volatile( \
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" mrrc p15, 0, %0, %1, c2 @ read TTBR0\n" \
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" mov %1, %2, lsl #(48 - 32) @ set ASID\n" \
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" mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" \
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: "=&r" (ttbl), "=&r" (ttbh) \
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: "r" (asid & ~ASID_MASK)); \
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}
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#else
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#define cpu_set_asid(asid) \
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asm(" mcr p15, 0, %0, c13, c0, 1\n" : : "r" (asid))
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#endif
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/*
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* We fork()ed a process, and we need a new context for the child
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* to run in. We reserve version 0 for initial tasks so we will
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* always allocate an ASID. The ASID 0 is reserved for the TTBR
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* register changing sequence.
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*/
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void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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mm->context.id = 0;
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raw_spin_lock_init(&mm->context.id_lock);
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}
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static void flush_context(void)
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{
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/* set the reserved ASID before flushing the TLB */
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cpu_set_asid(0);
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isb();
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local_flush_tlb_all();
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if (icache_is_vivt_asid_tagged()) {
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__flush_icache_all();
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dsb();
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}
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}
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#ifdef CONFIG_SMP
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static void set_mm_context(struct mm_struct *mm, unsigned int asid)
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{
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unsigned long flags;
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/*
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* Locking needed for multi-threaded applications where the
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* same mm->context.id could be set from different CPUs during
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* the broadcast. This function is also called via IPI so the
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* mm->context.id_lock has to be IRQ-safe.
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*/
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raw_spin_lock_irqsave(&mm->context.id_lock, flags);
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if (likely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) {
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/*
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* Old version of ASID found. Set the new one and
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* reset mm_cpumask(mm).
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*/
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mm->context.id = asid;
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cpumask_clear(mm_cpumask(mm));
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}
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raw_spin_unlock_irqrestore(&mm->context.id_lock, flags);
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/*
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* Set the mm_cpumask(mm) bit for the current CPU.
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*/
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
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}
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/*
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* Reset the ASID on the current CPU. This function call is broadcast
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* from the CPU handling the ASID rollover and holding cpu_asid_lock.
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*/
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static void reset_context(void *info)
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{
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unsigned int asid;
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unsigned int cpu = smp_processor_id();
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struct mm_struct *mm = per_cpu(current_mm, cpu);
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/*
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* Check if a current_mm was set on this CPU as it might still
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* be in the early booting stages and using the reserved ASID.
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*/
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if (!mm)
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return;
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smp_rmb();
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asid = cpu_last_asid + cpu + 1;
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flush_context();
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set_mm_context(mm, asid);
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/* set the new ASID */
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cpu_set_asid(mm->context.id);
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isb();
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}
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#else
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static inline void set_mm_context(struct mm_struct *mm, unsigned int asid)
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{
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mm->context.id = asid;
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cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
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}
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#endif
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void __new_context(struct mm_struct *mm)
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{
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unsigned int asid;
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raw_spin_lock(&cpu_asid_lock);
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#ifdef CONFIG_SMP
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/*
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* Check the ASID again, in case the change was broadcast from
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* another CPU before we acquired the lock.
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*/
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if (unlikely(((mm->context.id ^ cpu_last_asid) >> ASID_BITS) == 0)) {
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
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raw_spin_unlock(&cpu_asid_lock);
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return;
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}
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#endif
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/*
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* At this point, it is guaranteed that the current mm (with
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* an old ASID) isn't active on any other CPU since the ASIDs
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* are changed simultaneously via IPI.
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*/
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asid = ++cpu_last_asid;
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if (asid == 0)
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asid = cpu_last_asid = ASID_FIRST_VERSION;
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/*
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* If we've used up all our ASIDs, we need
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* to start a new version and flush the TLB.
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*/
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if (unlikely((asid & ~ASID_MASK) == 0)) {
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asid = cpu_last_asid + smp_processor_id() + 1;
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flush_context();
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#ifdef CONFIG_SMP
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smp_wmb();
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smp_call_function(reset_context, NULL, 1);
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#endif
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cpu_last_asid += NR_CPUS;
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}
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set_mm_context(mm, asid);
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raw_spin_unlock(&cpu_asid_lock);
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}
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