![Linus Torvalds](/assets/img/avatar_default.png)
Pull more ARM updates from Russell King. This got a fair number of conflicts with the <asm/system.h> split, but also with some other sparse-irq and header file include cleanups. They all looked pretty trivial, though. * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (59 commits) ARM: fix Kconfig warning for HAVE_BPF_JIT ARM: 7361/1: provide XIP_VIRT_ADDR for no-MMU builds ARM: 7349/1: integrator: convert to sparse irqs ARM: 7259/3: net: JIT compiler for packet filters ARM: 7334/1: add jump label support ARM: 7333/2: jump label: detect %c support for ARM ARM: 7338/1: add support for early console output via semihosting ARM: use set_current_blocked() and block_sigmask() ARM: exec: remove redundant set_fs(USER_DS) ARM: 7332/1: extract out code patch function from kprobes ARM: 7331/1: extract out insn generation code from ftrace ARM: 7330/1: ftrace: use canonical Thumb-2 wide instruction format ARM: 7351/1: ftrace: remove useless memory checks ARM: 7316/1: kexec: EOI active and mask all interrupts in kexec crash path ARM: Versatile Express: add NO_IOPORT ARM: get rid of asm/irq.h in asm/prom.h ARM: 7319/1: Print debug info for SIGBUS in user faults ARM: 7318/1: gic: refactor irq_start assignment ARM: 7317/1: irq: avoid NULL check in for_each_irq_desc loop ARM: 7315/1: perf: add support for the Cortex-A7 PMU ...
1135 lines
30 KiB
C
1135 lines
30 KiB
C
/*
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* linux/arch/arm/mm/mmu.c
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*
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* Copyright (C) 1995-2005 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/mman.h>
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#include <linux/nodemask.h>
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#include <linux/memblock.h>
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#include <linux/fs.h>
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#include <linux/vmalloc.h>
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#include <asm/sections.h>
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#include <asm/cachetype.h>
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#include <asm/setup.h>
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#include <asm/sizes.h>
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#include <asm/smp_plat.h>
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#include <asm/tlb.h>
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#include <asm/highmem.h>
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#include <asm/system_info.h>
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#include <asm/traps.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "mm.h"
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/*
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* empty_zero_page is a special page that is used for
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* zero-initialized data and COW.
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*/
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struct page *empty_zero_page;
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EXPORT_SYMBOL(empty_zero_page);
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/*
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* The pmd table for the upper-most set of pages.
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*/
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pmd_t *top_pmd;
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#define CPOLICY_UNCACHED 0
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#define CPOLICY_BUFFERED 1
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#define CPOLICY_WRITETHROUGH 2
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#define CPOLICY_WRITEBACK 3
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#define CPOLICY_WRITEALLOC 4
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static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
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static unsigned int ecc_mask __initdata = 0;
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pgprot_t pgprot_user;
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pgprot_t pgprot_kernel;
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EXPORT_SYMBOL(pgprot_user);
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EXPORT_SYMBOL(pgprot_kernel);
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struct cachepolicy {
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const char policy[16];
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unsigned int cr_mask;
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pmdval_t pmd;
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pteval_t pte;
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};
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static struct cachepolicy cache_policies[] __initdata = {
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{
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.policy = "uncached",
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.cr_mask = CR_W|CR_C,
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.pmd = PMD_SECT_UNCACHED,
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.pte = L_PTE_MT_UNCACHED,
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}, {
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.policy = "buffered",
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.cr_mask = CR_C,
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.pmd = PMD_SECT_BUFFERED,
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.pte = L_PTE_MT_BUFFERABLE,
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}, {
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.policy = "writethrough",
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.cr_mask = 0,
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.pmd = PMD_SECT_WT,
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.pte = L_PTE_MT_WRITETHROUGH,
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}, {
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.policy = "writeback",
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.cr_mask = 0,
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.pmd = PMD_SECT_WB,
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.pte = L_PTE_MT_WRITEBACK,
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}, {
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.policy = "writealloc",
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.cr_mask = 0,
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.pmd = PMD_SECT_WBWA,
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.pte = L_PTE_MT_WRITEALLOC,
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}
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};
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/*
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* These are useful for identifying cache coherency
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* problems by allowing the cache or the cache and
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* writebuffer to be turned off. (Note: the write
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* buffer should not be on and the cache off).
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*/
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static int __init early_cachepolicy(char *p)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
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int len = strlen(cache_policies[i].policy);
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if (memcmp(p, cache_policies[i].policy, len) == 0) {
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cachepolicy = i;
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cr_alignment &= ~cache_policies[i].cr_mask;
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cr_no_alignment &= ~cache_policies[i].cr_mask;
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break;
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}
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}
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if (i == ARRAY_SIZE(cache_policies))
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printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
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/*
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* This restriction is partly to do with the way we boot; it is
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* unpredictable to have memory mapped using two different sets of
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* memory attributes (shared, type, and cache attribs). We can not
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* change these attributes once the initial assembly has setup the
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* page tables.
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*/
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if (cpu_architecture() >= CPU_ARCH_ARMv6) {
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printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
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cachepolicy = CPOLICY_WRITEBACK;
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}
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flush_cache_all();
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set_cr(cr_alignment);
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return 0;
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}
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early_param("cachepolicy", early_cachepolicy);
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static int __init early_nocache(char *__unused)
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{
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char *p = "buffered";
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printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
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early_cachepolicy(p);
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return 0;
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}
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early_param("nocache", early_nocache);
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static int __init early_nowrite(char *__unused)
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{
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char *p = "uncached";
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printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
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early_cachepolicy(p);
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return 0;
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}
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early_param("nowb", early_nowrite);
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#ifndef CONFIG_ARM_LPAE
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static int __init early_ecc(char *p)
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{
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if (memcmp(p, "on", 2) == 0)
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ecc_mask = PMD_PROTECTION;
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else if (memcmp(p, "off", 3) == 0)
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ecc_mask = 0;
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return 0;
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}
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early_param("ecc", early_ecc);
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#endif
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static int __init noalign_setup(char *__unused)
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{
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cr_alignment &= ~CR_A;
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cr_no_alignment &= ~CR_A;
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set_cr(cr_alignment);
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return 1;
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}
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__setup("noalign", noalign_setup);
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#ifndef CONFIG_SMP
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void adjust_cr(unsigned long mask, unsigned long set)
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{
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unsigned long flags;
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mask &= ~CR_A;
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set &= mask;
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local_irq_save(flags);
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cr_no_alignment = (cr_no_alignment & ~mask) | set;
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cr_alignment = (cr_alignment & ~mask) | set;
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set_cr((get_cr() & ~mask) | set);
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local_irq_restore(flags);
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}
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#endif
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#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
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#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
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static struct mem_type mem_types[] = {
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[MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
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L_PTE_SHARED,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE,
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_CACHED] = { /* ioremap_cached */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_WC] = { /* ioremap_wc */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE,
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.domain = DOMAIN_IO,
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},
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[MT_UNCACHED] = {
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.prot_pte = PROT_PTE_DEVICE,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
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.domain = DOMAIN_IO,
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},
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[MT_CACHECLEAN] = {
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
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.domain = DOMAIN_KERNEL,
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},
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#ifndef CONFIG_ARM_LPAE
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[MT_MINICLEAN] = {
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
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.domain = DOMAIN_KERNEL,
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},
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#endif
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[MT_LOW_VECTORS] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_RDONLY,
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.prot_l1 = PMD_TYPE_TABLE,
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.domain = DOMAIN_USER,
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},
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[MT_HIGH_VECTORS] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_USER | L_PTE_RDONLY,
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.prot_l1 = PMD_TYPE_TABLE,
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.domain = DOMAIN_USER,
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},
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[MT_MEMORY] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
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.domain = DOMAIN_KERNEL,
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},
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[MT_ROM] = {
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.prot_sect = PMD_TYPE_SECT,
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.domain = DOMAIN_KERNEL,
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},
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[MT_MEMORY_NONCACHED] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_MT_BUFFERABLE,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
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.domain = DOMAIN_KERNEL,
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},
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[MT_MEMORY_DTCM] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_XN,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
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.domain = DOMAIN_KERNEL,
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},
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[MT_MEMORY_ITCM] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
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.prot_l1 = PMD_TYPE_TABLE,
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.domain = DOMAIN_KERNEL,
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},
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[MT_MEMORY_SO] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_MT_UNCACHED,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
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PMD_SECT_UNCACHED | PMD_SECT_XN,
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.domain = DOMAIN_KERNEL,
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},
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};
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const struct mem_type *get_mem_type(unsigned int type)
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{
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return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
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}
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EXPORT_SYMBOL(get_mem_type);
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/*
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* Adjust the PMD section entries according to the CPU in use.
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*/
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static void __init build_mem_type_table(void)
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{
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struct cachepolicy *cp;
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unsigned int cr = get_cr();
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pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
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int cpu_arch = cpu_architecture();
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int i;
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if (cpu_arch < CPU_ARCH_ARMv6) {
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#if defined(CONFIG_CPU_DCACHE_DISABLE)
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if (cachepolicy > CPOLICY_BUFFERED)
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cachepolicy = CPOLICY_BUFFERED;
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#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
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if (cachepolicy > CPOLICY_WRITETHROUGH)
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cachepolicy = CPOLICY_WRITETHROUGH;
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#endif
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}
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if (cpu_arch < CPU_ARCH_ARMv5) {
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if (cachepolicy >= CPOLICY_WRITEALLOC)
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cachepolicy = CPOLICY_WRITEBACK;
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ecc_mask = 0;
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}
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if (is_smp())
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cachepolicy = CPOLICY_WRITEALLOC;
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/*
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* Strip out features not present on earlier architectures.
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* Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
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* without extended page tables don't have the 'Shared' bit.
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*/
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if (cpu_arch < CPU_ARCH_ARMv5)
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for (i = 0; i < ARRAY_SIZE(mem_types); i++)
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mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
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if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
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for (i = 0; i < ARRAY_SIZE(mem_types); i++)
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mem_types[i].prot_sect &= ~PMD_SECT_S;
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/*
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* ARMv5 and lower, bit 4 must be set for page tables (was: cache
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* "update-able on write" bit on ARM610). However, Xscale and
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* Xscale3 require this bit to be cleared.
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*/
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if (cpu_is_xscale() || cpu_is_xsc3()) {
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for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
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mem_types[i].prot_sect &= ~PMD_BIT4;
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mem_types[i].prot_l1 &= ~PMD_BIT4;
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}
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} else if (cpu_arch < CPU_ARCH_ARMv6) {
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for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
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if (mem_types[i].prot_l1)
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mem_types[i].prot_l1 |= PMD_BIT4;
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if (mem_types[i].prot_sect)
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mem_types[i].prot_sect |= PMD_BIT4;
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}
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}
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/*
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* Mark the device areas according to the CPU/architecture.
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*/
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if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
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if (!cpu_is_xsc3()) {
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/*
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* Mark device regions on ARMv6+ as execute-never
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* to prevent speculative instruction fetches.
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*/
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mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
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mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
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mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
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mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
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}
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if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
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/*
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* For ARMv7 with TEX remapping,
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* - shared device is SXCB=1100
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* - nonshared device is SXCB=0100
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* - write combine device mem is SXCB=0001
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* (Uncached Normal memory)
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*/
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mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
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mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
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mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
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} else if (cpu_is_xsc3()) {
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/*
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* For Xscale3,
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* - shared device is TEXCB=00101
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* - nonshared device is TEXCB=01000
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* - write combine device mem is TEXCB=00100
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* (Inner/Outer Uncacheable in xsc3 parlance)
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*/
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mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
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mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
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mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
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} else {
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/*
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* For ARMv6 and ARMv7 without TEX remapping,
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* - shared device is TEXCB=00001
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* - nonshared device is TEXCB=01000
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* - write combine device mem is TEXCB=00100
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* (Uncached Normal in ARMv6 parlance).
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*/
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mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
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mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
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mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
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}
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} else {
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/*
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* On others, write combining is "Uncached/Buffered"
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*/
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mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
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}
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/*
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* Now deal with the memory-type mappings
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*/
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cp = &cache_policies[cachepolicy];
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vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
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/*
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* Only use write-through for non-SMP systems
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*/
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if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
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vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
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/*
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* Enable CPU-specific coherency if supported.
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* (Only available on XSC3 at the moment.)
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*/
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if (arch_is_coherent() && cpu_is_xsc3()) {
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mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
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mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
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mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
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mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
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}
|
|
/*
|
|
* ARMv6 and above have extended page tables.
|
|
*/
|
|
if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
|
|
#ifndef CONFIG_ARM_LPAE
|
|
/*
|
|
* Mark cache clean areas and XIP ROM read only
|
|
* from SVC mode and no access from userspace.
|
|
*/
|
|
mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
|
|
mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
|
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
|
|
#endif
|
|
|
|
if (is_smp()) {
|
|
/*
|
|
* Mark memory with the "shared" attribute
|
|
* for SMP systems
|
|
*/
|
|
user_pgprot |= L_PTE_SHARED;
|
|
kern_pgprot |= L_PTE_SHARED;
|
|
vecs_pgprot |= L_PTE_SHARED;
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
|
|
mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
|
|
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
|
|
mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
|
|
mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
|
|
mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
|
|
mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Non-cacheable Normal - intended for memory areas that must
|
|
* not cause dirty cache line writebacks when used
|
|
*/
|
|
if (cpu_arch >= CPU_ARCH_ARMv6) {
|
|
if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
|
|
/* Non-cacheable Normal is XCB = 001 */
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |=
|
|
PMD_SECT_BUFFERED;
|
|
} else {
|
|
/* For both ARMv6 and non-TEX-remapping ARMv7 */
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |=
|
|
PMD_SECT_TEX(1);
|
|
}
|
|
} else {
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
|
|
}
|
|
|
|
#ifdef CONFIG_ARM_LPAE
|
|
/*
|
|
* Do not generate access flag faults for the kernel mappings.
|
|
*/
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
|
|
mem_types[i].prot_pte |= PTE_EXT_AF;
|
|
mem_types[i].prot_sect |= PMD_SECT_AF;
|
|
}
|
|
kern_pgprot |= PTE_EXT_AF;
|
|
vecs_pgprot |= PTE_EXT_AF;
|
|
#endif
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
unsigned long v = pgprot_val(protection_map[i]);
|
|
protection_map[i] = __pgprot(v | user_pgprot);
|
|
}
|
|
|
|
mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
|
|
mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
|
|
|
|
pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
|
|
pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
|
|
L_PTE_DIRTY | kern_pgprot);
|
|
|
|
mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
|
|
mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
|
|
mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
|
|
mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
|
|
mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
|
|
mem_types[MT_ROM].prot_sect |= cp->pmd;
|
|
|
|
switch (cp->pmd) {
|
|
case PMD_SECT_WT:
|
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
|
|
break;
|
|
case PMD_SECT_WB:
|
|
case PMD_SECT_WBWA:
|
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
|
|
break;
|
|
}
|
|
printk("Memory policy: ECC %sabled, Data cache %s\n",
|
|
ecc_mask ? "en" : "dis", cp->policy);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
|
|
struct mem_type *t = &mem_types[i];
|
|
if (t->prot_l1)
|
|
t->prot_l1 |= PMD_DOMAIN(t->domain);
|
|
if (t->prot_sect)
|
|
t->prot_sect |= PMD_DOMAIN(t->domain);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
|
|
pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
|
unsigned long size, pgprot_t vma_prot)
|
|
{
|
|
if (!pfn_valid(pfn))
|
|
return pgprot_noncached(vma_prot);
|
|
else if (file->f_flags & O_SYNC)
|
|
return pgprot_writecombine(vma_prot);
|
|
return vma_prot;
|
|
}
|
|
EXPORT_SYMBOL(phys_mem_access_prot);
|
|
#endif
|
|
|
|
#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
|
|
|
|
static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
|
|
{
|
|
void *ptr = __va(memblock_alloc(sz, align));
|
|
memset(ptr, 0, sz);
|
|
return ptr;
|
|
}
|
|
|
|
static void __init *early_alloc(unsigned long sz)
|
|
{
|
|
return early_alloc_aligned(sz, sz);
|
|
}
|
|
|
|
static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
|
|
{
|
|
if (pmd_none(*pmd)) {
|
|
pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
|
|
__pmd_populate(pmd, __pa(pte), prot);
|
|
}
|
|
BUG_ON(pmd_bad(*pmd));
|
|
return pte_offset_kernel(pmd, addr);
|
|
}
|
|
|
|
static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
|
|
unsigned long end, unsigned long pfn,
|
|
const struct mem_type *type)
|
|
{
|
|
pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
|
|
do {
|
|
set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
|
|
pfn++;
|
|
} while (pte++, addr += PAGE_SIZE, addr != end);
|
|
}
|
|
|
|
static void __init alloc_init_section(pud_t *pud, unsigned long addr,
|
|
unsigned long end, phys_addr_t phys,
|
|
const struct mem_type *type)
|
|
{
|
|
pmd_t *pmd = pmd_offset(pud, addr);
|
|
|
|
/*
|
|
* Try a section mapping - end, addr and phys must all be aligned
|
|
* to a section boundary. Note that PMDs refer to the individual
|
|
* L1 entries, whereas PGDs refer to a group of L1 entries making
|
|
* up one logical pointer to an L2 table.
|
|
*/
|
|
if (((addr | end | phys) & ~SECTION_MASK) == 0) {
|
|
pmd_t *p = pmd;
|
|
|
|
#ifndef CONFIG_ARM_LPAE
|
|
if (addr & SECTION_SIZE)
|
|
pmd++;
|
|
#endif
|
|
|
|
do {
|
|
*pmd = __pmd(phys | type->prot_sect);
|
|
phys += SECTION_SIZE;
|
|
} while (pmd++, addr += SECTION_SIZE, addr != end);
|
|
|
|
flush_pmd_entry(p);
|
|
} else {
|
|
/*
|
|
* No need to loop; pte's aren't interested in the
|
|
* individual L1 entries.
|
|
*/
|
|
alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
|
|
}
|
|
}
|
|
|
|
static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
|
|
unsigned long phys, const struct mem_type *type)
|
|
{
|
|
pud_t *pud = pud_offset(pgd, addr);
|
|
unsigned long next;
|
|
|
|
do {
|
|
next = pud_addr_end(addr, end);
|
|
alloc_init_section(pud, addr, next, phys, type);
|
|
phys += next - addr;
|
|
} while (pud++, addr = next, addr != end);
|
|
}
|
|
|
|
#ifndef CONFIG_ARM_LPAE
|
|
static void __init create_36bit_mapping(struct map_desc *md,
|
|
const struct mem_type *type)
|
|
{
|
|
unsigned long addr, length, end;
|
|
phys_addr_t phys;
|
|
pgd_t *pgd;
|
|
|
|
addr = md->virtual;
|
|
phys = __pfn_to_phys(md->pfn);
|
|
length = PAGE_ALIGN(md->length);
|
|
|
|
if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
|
|
printk(KERN_ERR "MM: CPU does not support supersection "
|
|
"mapping for 0x%08llx at 0x%08lx\n",
|
|
(long long)__pfn_to_phys((u64)md->pfn), addr);
|
|
return;
|
|
}
|
|
|
|
/* N.B. ARMv6 supersections are only defined to work with domain 0.
|
|
* Since domain assignments can in fact be arbitrary, the
|
|
* 'domain == 0' check below is required to insure that ARMv6
|
|
* supersections are only allocated for domain 0 regardless
|
|
* of the actual domain assignments in use.
|
|
*/
|
|
if (type->domain) {
|
|
printk(KERN_ERR "MM: invalid domain in supersection "
|
|
"mapping for 0x%08llx at 0x%08lx\n",
|
|
(long long)__pfn_to_phys((u64)md->pfn), addr);
|
|
return;
|
|
}
|
|
|
|
if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
|
|
printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
|
|
" at 0x%08lx invalid alignment\n",
|
|
(long long)__pfn_to_phys((u64)md->pfn), addr);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Shift bits [35:32] of address into bits [23:20] of PMD
|
|
* (See ARMv6 spec).
|
|
*/
|
|
phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
|
|
|
|
pgd = pgd_offset_k(addr);
|
|
end = addr + length;
|
|
do {
|
|
pud_t *pud = pud_offset(pgd, addr);
|
|
pmd_t *pmd = pmd_offset(pud, addr);
|
|
int i;
|
|
|
|
for (i = 0; i < 16; i++)
|
|
*pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
|
|
|
|
addr += SUPERSECTION_SIZE;
|
|
phys += SUPERSECTION_SIZE;
|
|
pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
|
|
} while (addr != end);
|
|
}
|
|
#endif /* !CONFIG_ARM_LPAE */
|
|
|
|
/*
|
|
* Create the page directory entries and any necessary
|
|
* page tables for the mapping specified by `md'. We
|
|
* are able to cope here with varying sizes and address
|
|
* offsets, and we take full advantage of sections and
|
|
* supersections.
|
|
*/
|
|
static void __init create_mapping(struct map_desc *md)
|
|
{
|
|
unsigned long addr, length, end;
|
|
phys_addr_t phys;
|
|
const struct mem_type *type;
|
|
pgd_t *pgd;
|
|
|
|
if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
|
|
printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
|
|
" at 0x%08lx in user region\n",
|
|
(long long)__pfn_to_phys((u64)md->pfn), md->virtual);
|
|
return;
|
|
}
|
|
|
|
if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
|
|
md->virtual >= PAGE_OFFSET &&
|
|
(md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
|
|
printk(KERN_WARNING "BUG: mapping for 0x%08llx"
|
|
" at 0x%08lx out of vmalloc space\n",
|
|
(long long)__pfn_to_phys((u64)md->pfn), md->virtual);
|
|
}
|
|
|
|
type = &mem_types[md->type];
|
|
|
|
#ifndef CONFIG_ARM_LPAE
|
|
/*
|
|
* Catch 36-bit addresses
|
|
*/
|
|
if (md->pfn >= 0x100000) {
|
|
create_36bit_mapping(md, type);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
addr = md->virtual & PAGE_MASK;
|
|
phys = __pfn_to_phys(md->pfn);
|
|
length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
|
|
|
|
if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
|
|
printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
|
|
"be mapped using pages, ignoring.\n",
|
|
(long long)__pfn_to_phys(md->pfn), addr);
|
|
return;
|
|
}
|
|
|
|
pgd = pgd_offset_k(addr);
|
|
end = addr + length;
|
|
do {
|
|
unsigned long next = pgd_addr_end(addr, end);
|
|
|
|
alloc_init_pud(pgd, addr, next, phys, type);
|
|
|
|
phys += next - addr;
|
|
addr = next;
|
|
} while (pgd++, addr != end);
|
|
}
|
|
|
|
/*
|
|
* Create the architecture specific mappings
|
|
*/
|
|
void __init iotable_init(struct map_desc *io_desc, int nr)
|
|
{
|
|
struct map_desc *md;
|
|
struct vm_struct *vm;
|
|
|
|
if (!nr)
|
|
return;
|
|
|
|
vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
|
|
|
|
for (md = io_desc; nr; md++, nr--) {
|
|
create_mapping(md);
|
|
vm->addr = (void *)(md->virtual & PAGE_MASK);
|
|
vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
|
|
vm->phys_addr = __pfn_to_phys(md->pfn);
|
|
vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
|
|
vm->flags |= VM_ARM_MTYPE(md->type);
|
|
vm->caller = iotable_init;
|
|
vm_area_add_early(vm++);
|
|
}
|
|
}
|
|
|
|
static void * __initdata vmalloc_min =
|
|
(void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
|
|
|
|
/*
|
|
* vmalloc=size forces the vmalloc area to be exactly 'size'
|
|
* bytes. This can be used to increase (or decrease) the vmalloc
|
|
* area - the default is 240m.
|
|
*/
|
|
static int __init early_vmalloc(char *arg)
|
|
{
|
|
unsigned long vmalloc_reserve = memparse(arg, NULL);
|
|
|
|
if (vmalloc_reserve < SZ_16M) {
|
|
vmalloc_reserve = SZ_16M;
|
|
printk(KERN_WARNING
|
|
"vmalloc area too small, limiting to %luMB\n",
|
|
vmalloc_reserve >> 20);
|
|
}
|
|
|
|
if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
|
|
vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
|
|
printk(KERN_WARNING
|
|
"vmalloc area is too big, limiting to %luMB\n",
|
|
vmalloc_reserve >> 20);
|
|
}
|
|
|
|
vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
|
|
return 0;
|
|
}
|
|
early_param("vmalloc", early_vmalloc);
|
|
|
|
static phys_addr_t lowmem_limit __initdata = 0;
|
|
|
|
void __init sanity_check_meminfo(void)
|
|
{
|
|
int i, j, highmem = 0;
|
|
|
|
for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
|
|
struct membank *bank = &meminfo.bank[j];
|
|
*bank = meminfo.bank[i];
|
|
|
|
if (bank->start > ULONG_MAX)
|
|
highmem = 1;
|
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
if (__va(bank->start) >= vmalloc_min ||
|
|
__va(bank->start) < (void *)PAGE_OFFSET)
|
|
highmem = 1;
|
|
|
|
bank->highmem = highmem;
|
|
|
|
/*
|
|
* Split those memory banks which are partially overlapping
|
|
* the vmalloc area greatly simplifying things later.
|
|
*/
|
|
if (!highmem && __va(bank->start) < vmalloc_min &&
|
|
bank->size > vmalloc_min - __va(bank->start)) {
|
|
if (meminfo.nr_banks >= NR_BANKS) {
|
|
printk(KERN_CRIT "NR_BANKS too low, "
|
|
"ignoring high memory\n");
|
|
} else {
|
|
memmove(bank + 1, bank,
|
|
(meminfo.nr_banks - i) * sizeof(*bank));
|
|
meminfo.nr_banks++;
|
|
i++;
|
|
bank[1].size -= vmalloc_min - __va(bank->start);
|
|
bank[1].start = __pa(vmalloc_min - 1) + 1;
|
|
bank[1].highmem = highmem = 1;
|
|
j++;
|
|
}
|
|
bank->size = vmalloc_min - __va(bank->start);
|
|
}
|
|
#else
|
|
bank->highmem = highmem;
|
|
|
|
/*
|
|
* Highmem banks not allowed with !CONFIG_HIGHMEM.
|
|
*/
|
|
if (highmem) {
|
|
printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
|
|
"(!CONFIG_HIGHMEM).\n",
|
|
(unsigned long long)bank->start,
|
|
(unsigned long long)bank->start + bank->size - 1);
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* Check whether this memory bank would entirely overlap
|
|
* the vmalloc area.
|
|
*/
|
|
if (__va(bank->start) >= vmalloc_min ||
|
|
__va(bank->start) < (void *)PAGE_OFFSET) {
|
|
printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
|
|
"(vmalloc region overlap).\n",
|
|
(unsigned long long)bank->start,
|
|
(unsigned long long)bank->start + bank->size - 1);
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* Check whether this memory bank would partially overlap
|
|
* the vmalloc area.
|
|
*/
|
|
if (__va(bank->start + bank->size) > vmalloc_min ||
|
|
__va(bank->start + bank->size) < __va(bank->start)) {
|
|
unsigned long newsize = vmalloc_min - __va(bank->start);
|
|
printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
|
|
"to -%.8llx (vmalloc region overlap).\n",
|
|
(unsigned long long)bank->start,
|
|
(unsigned long long)bank->start + bank->size - 1,
|
|
(unsigned long long)bank->start + newsize - 1);
|
|
bank->size = newsize;
|
|
}
|
|
#endif
|
|
if (!bank->highmem && bank->start + bank->size > lowmem_limit)
|
|
lowmem_limit = bank->start + bank->size;
|
|
|
|
j++;
|
|
}
|
|
#ifdef CONFIG_HIGHMEM
|
|
if (highmem) {
|
|
const char *reason = NULL;
|
|
|
|
if (cache_is_vipt_aliasing()) {
|
|
/*
|
|
* Interactions between kmap and other mappings
|
|
* make highmem support with aliasing VIPT caches
|
|
* rather difficult.
|
|
*/
|
|
reason = "with VIPT aliasing cache";
|
|
}
|
|
if (reason) {
|
|
printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
|
|
reason);
|
|
while (j > 0 && meminfo.bank[j - 1].highmem)
|
|
j--;
|
|
}
|
|
}
|
|
#endif
|
|
meminfo.nr_banks = j;
|
|
high_memory = __va(lowmem_limit - 1) + 1;
|
|
memblock_set_current_limit(lowmem_limit);
|
|
}
|
|
|
|
static inline void prepare_page_table(void)
|
|
{
|
|
unsigned long addr;
|
|
phys_addr_t end;
|
|
|
|
/*
|
|
* Clear out all the mappings below the kernel image.
|
|
*/
|
|
for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
#ifdef CONFIG_XIP_KERNEL
|
|
/* The XIP kernel is mapped in the module area -- skip over it */
|
|
addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
|
|
#endif
|
|
for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
/*
|
|
* Find the end of the first block of lowmem.
|
|
*/
|
|
end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
|
|
if (end >= lowmem_limit)
|
|
end = lowmem_limit;
|
|
|
|
/*
|
|
* Clear out all the kernel space mappings, except for the first
|
|
* memory bank, up to the vmalloc region.
|
|
*/
|
|
for (addr = __phys_to_virt(end);
|
|
addr < VMALLOC_START; addr += PMD_SIZE)
|
|
pmd_clear(pmd_off_k(addr));
|
|
}
|
|
|
|
#ifdef CONFIG_ARM_LPAE
|
|
/* the first page is reserved for pgd */
|
|
#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
|
|
PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
|
|
#else
|
|
#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
|
|
#endif
|
|
|
|
/*
|
|
* Reserve the special regions of memory
|
|
*/
|
|
void __init arm_mm_memblock_reserve(void)
|
|
{
|
|
/*
|
|
* Reserve the page tables. These are already in use,
|
|
* and can only be in node 0.
|
|
*/
|
|
memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
|
|
|
|
#ifdef CONFIG_SA1111
|
|
/*
|
|
* Because of the SA1111 DMA bug, we want to preserve our
|
|
* precious DMA-able memory...
|
|
*/
|
|
memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Set up the device mappings. Since we clear out the page tables for all
|
|
* mappings above VMALLOC_START, we will remove any debug device mappings.
|
|
* This means you have to be careful how you debug this function, or any
|
|
* called function. This means you can't use any function or debugging
|
|
* method which may touch any device, otherwise the kernel _will_ crash.
|
|
*/
|
|
static void __init devicemaps_init(struct machine_desc *mdesc)
|
|
{
|
|
struct map_desc map;
|
|
unsigned long addr;
|
|
void *vectors;
|
|
|
|
/*
|
|
* Allocate the vector page early.
|
|
*/
|
|
vectors = early_alloc(PAGE_SIZE);
|
|
|
|
early_trap_init(vectors);
|
|
|
|
for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
/*
|
|
* Map the kernel if it is XIP.
|
|
* It is always first in the modulearea.
|
|
*/
|
|
#ifdef CONFIG_XIP_KERNEL
|
|
map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
|
|
map.virtual = MODULES_VADDR;
|
|
map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
|
|
map.type = MT_ROM;
|
|
create_mapping(&map);
|
|
#endif
|
|
|
|
/*
|
|
* Map the cache flushing regions.
|
|
*/
|
|
#ifdef FLUSH_BASE
|
|
map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
|
|
map.virtual = FLUSH_BASE;
|
|
map.length = SZ_1M;
|
|
map.type = MT_CACHECLEAN;
|
|
create_mapping(&map);
|
|
#endif
|
|
#ifdef FLUSH_BASE_MINICACHE
|
|
map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
|
|
map.virtual = FLUSH_BASE_MINICACHE;
|
|
map.length = SZ_1M;
|
|
map.type = MT_MINICLEAN;
|
|
create_mapping(&map);
|
|
#endif
|
|
|
|
/*
|
|
* Create a mapping for the machine vectors at the high-vectors
|
|
* location (0xffff0000). If we aren't using high-vectors, also
|
|
* create a mapping at the low-vectors virtual address.
|
|
*/
|
|
map.pfn = __phys_to_pfn(virt_to_phys(vectors));
|
|
map.virtual = 0xffff0000;
|
|
map.length = PAGE_SIZE;
|
|
map.type = MT_HIGH_VECTORS;
|
|
create_mapping(&map);
|
|
|
|
if (!vectors_high()) {
|
|
map.virtual = 0;
|
|
map.type = MT_LOW_VECTORS;
|
|
create_mapping(&map);
|
|
}
|
|
|
|
/*
|
|
* Ask the machine support to map in the statically mapped devices.
|
|
*/
|
|
if (mdesc->map_io)
|
|
mdesc->map_io();
|
|
|
|
/*
|
|
* Finally flush the caches and tlb to ensure that we're in a
|
|
* consistent state wrt the writebuffer. This also ensures that
|
|
* any write-allocated cache lines in the vector page are written
|
|
* back. After this point, we can start to touch devices again.
|
|
*/
|
|
local_flush_tlb_all();
|
|
flush_cache_all();
|
|
}
|
|
|
|
static void __init kmap_init(void)
|
|
{
|
|
#ifdef CONFIG_HIGHMEM
|
|
pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
|
|
PKMAP_BASE, _PAGE_KERNEL_TABLE);
|
|
#endif
|
|
}
|
|
|
|
static void __init map_lowmem(void)
|
|
{
|
|
struct memblock_region *reg;
|
|
|
|
/* Map all the lowmem memory banks. */
|
|
for_each_memblock(memory, reg) {
|
|
phys_addr_t start = reg->base;
|
|
phys_addr_t end = start + reg->size;
|
|
struct map_desc map;
|
|
|
|
if (end > lowmem_limit)
|
|
end = lowmem_limit;
|
|
if (start >= end)
|
|
break;
|
|
|
|
map.pfn = __phys_to_pfn(start);
|
|
map.virtual = __phys_to_virt(start);
|
|
map.length = end - start;
|
|
map.type = MT_MEMORY;
|
|
|
|
create_mapping(&map);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* paging_init() sets up the page tables, initialises the zone memory
|
|
* maps, and sets up the zero page, bad page and bad page tables.
|
|
*/
|
|
void __init paging_init(struct machine_desc *mdesc)
|
|
{
|
|
void *zero_page;
|
|
|
|
memblock_set_current_limit(lowmem_limit);
|
|
|
|
build_mem_type_table();
|
|
prepare_page_table();
|
|
map_lowmem();
|
|
devicemaps_init(mdesc);
|
|
kmap_init();
|
|
|
|
top_pmd = pmd_off_k(0xffff0000);
|
|
|
|
/* allocate the zero page. */
|
|
zero_page = early_alloc(PAGE_SIZE);
|
|
|
|
bootmem_init();
|
|
|
|
empty_zero_page = virt_to_page(zero_page);
|
|
__flush_dcache_page(NULL, empty_zero_page);
|
|
}
|