![Yoshihiro Shimoda](/assets/img/avatar_default.png)
The latest HW manual (Rev.0.55) shows us this UGCTRL2.VBUSSEL bit.
If the bit sets to 1, the VBUS drive is controlled by phy related
registers (called "UCOM Registers" on the manual). Since R-Car Gen3
environment will control VBUS by phy-rcar-gen3-usb2 driver,
the UGCTRL2.VBUSSEL bit should be set to 1. So, this patch fixes
the register's value. Otherwise, even if the ID pin indicates to
peripheral, the R-Car will output USBn_PWEN to 1 when a host driver
is running.
Fixes: de18757e27
("usb: renesas_usbhs: add R-Car Gen3 power control"
Cc: <stable@vger.kernel.org> # v4.6+
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
64 lines
1.6 KiB
C
64 lines
1.6 KiB
C
/*
|
|
* Renesas USB driver R-Car Gen. 3 initialization and power control
|
|
*
|
|
* Copyright (C) 2016 Renesas Electronics Corporation
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
*/
|
|
|
|
#include <linux/delay.h>
|
|
#include <linux/io.h>
|
|
#include "common.h"
|
|
#include "rcar3.h"
|
|
|
|
#define LPSTS 0x102
|
|
#define UGCTRL2 0x184 /* 32-bit register */
|
|
|
|
/* Low Power Status register (LPSTS) */
|
|
#define LPSTS_SUSPM 0x4000
|
|
|
|
/*
|
|
* USB General control register 2 (UGCTRL2)
|
|
* Remarks: bit[31:11] and bit[9:6] should be 0
|
|
*/
|
|
#define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
|
|
#define UGCTRL2_USB0SEL_OTG 0x00000030
|
|
#define UGCTRL2_VBUSSEL 0x00000400
|
|
|
|
static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data)
|
|
{
|
|
iowrite32(data, priv->base + reg);
|
|
}
|
|
|
|
static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
|
|
void __iomem *base, int enable)
|
|
{
|
|
struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
|
|
|
|
usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 | UGCTRL2_USB0SEL_OTG |
|
|
UGCTRL2_VBUSSEL);
|
|
|
|
if (enable) {
|
|
usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
|
|
/* The controller on R-Car Gen3 needs to wait up to 45 usec */
|
|
udelay(45);
|
|
} else {
|
|
usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int usbhs_rcar3_get_id(struct platform_device *pdev)
|
|
{
|
|
return USBHS_GADGET;
|
|
}
|
|
|
|
const struct renesas_usbhs_platform_callback usbhs_rcar3_ops = {
|
|
.power_ctrl = usbhs_rcar3_power_ctrl,
|
|
.get_id = usbhs_rcar3_get_id,
|
|
};
|