![Guo Ren](/assets/img/avatar_default.png)
The driver is for C-SKY SMP timer. It only supports oneshot event and 32bit overflow for clocksource. Per cpu core has one timer and all timers share one clock-counter-input from the same clocksource. This use mfcr&mtcr instructions to access the regs. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
174 lines
3.7 KiB
C
174 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/sched_clock.h>
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#include <linux/cpu.h>
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#include <linux/of_irq.h>
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#include <asm/reg_ops.h>
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#include "timer-of.h"
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#define PTIM_CCVR "cr<3, 14>"
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#define PTIM_CTLR "cr<0, 14>"
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#define PTIM_LVR "cr<6, 14>"
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#define PTIM_TSR "cr<1, 14>"
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static int csky_mptimer_irq;
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static int csky_mptimer_set_next_event(unsigned long delta,
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struct clock_event_device *ce)
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{
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mtcr(PTIM_LVR, delta);
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return 0;
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}
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static int csky_mptimer_shutdown(struct clock_event_device *ce)
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{
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mtcr(PTIM_CTLR, 0);
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return 0;
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}
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static int csky_mptimer_oneshot(struct clock_event_device *ce)
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{
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mtcr(PTIM_CTLR, 1);
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return 0;
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}
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static int csky_mptimer_oneshot_stopped(struct clock_event_device *ce)
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{
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mtcr(PTIM_CTLR, 0);
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return 0;
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}
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static DEFINE_PER_CPU(struct timer_of, csky_to) = {
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.flags = TIMER_OF_CLOCK,
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.clkevt = {
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.rating = 300,
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.features = CLOCK_EVT_FEAT_PERCPU |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = csky_mptimer_shutdown,
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.set_state_oneshot = csky_mptimer_oneshot,
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.set_state_oneshot_stopped = csky_mptimer_oneshot_stopped,
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.set_next_event = csky_mptimer_set_next_event,
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},
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};
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static irqreturn_t csky_timer_interrupt(int irq, void *dev)
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{
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struct timer_of *to = this_cpu_ptr(&csky_to);
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mtcr(PTIM_TSR, 0);
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to->clkevt.event_handler(&to->clkevt);
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return IRQ_HANDLED;
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}
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/*
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* clock event for percpu
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*/
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static int csky_mptimer_starting_cpu(unsigned int cpu)
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{
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struct timer_of *to = per_cpu_ptr(&csky_to, cpu);
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to->clkevt.cpumask = cpumask_of(cpu);
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clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
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2, ULONG_MAX);
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enable_percpu_irq(csky_mptimer_irq, 0);
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return 0;
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}
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static int csky_mptimer_dying_cpu(unsigned int cpu)
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{
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disable_percpu_irq(csky_mptimer_irq);
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return 0;
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}
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/*
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* clock source
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*/
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static u64 sched_clock_read(void)
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{
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return (u64)mfcr(PTIM_CCVR);
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}
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static u64 clksrc_read(struct clocksource *c)
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{
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return (u64)mfcr(PTIM_CCVR);
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}
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struct clocksource csky_clocksource = {
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.name = "csky",
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.rating = 400,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.read = clksrc_read,
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};
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static int __init csky_mptimer_init(struct device_node *np)
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{
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int ret, cpu, cpu_rollback;
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struct timer_of *to = NULL;
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/*
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* Csky_mptimer is designed for C-SKY SMP multi-processors and
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* every core has it's own private irq and regs for clkevt and
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* clksrc.
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*
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* The regs is accessed by cpu instruction: mfcr/mtcr instead of
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* mmio map style. So we needn't mmio-address in dts, but we still
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* need to give clk and irq number.
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*
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* We use private irq for the mptimer and irq number is the same
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* for every core. So we use request_percpu_irq() in timer_of_init.
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*/
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csky_mptimer_irq = irq_of_parse_and_map(np, 0);
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if (csky_mptimer_irq <= 0)
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return -EINVAL;
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ret = request_percpu_irq(csky_mptimer_irq, csky_timer_interrupt,
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"csky_mp_timer", &csky_to);
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if (ret)
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return -EINVAL;
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for_each_possible_cpu(cpu) {
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to = per_cpu_ptr(&csky_to, cpu);
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ret = timer_of_init(np, to);
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if (ret)
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goto rollback;
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}
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clocksource_register_hz(&csky_clocksource, timer_of_rate(to));
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sched_clock_register(sched_clock_read, 32, timer_of_rate(to));
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ret = cpuhp_setup_state(CPUHP_AP_CSKY_TIMER_STARTING,
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"clockevents/csky/timer:starting",
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csky_mptimer_starting_cpu,
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csky_mptimer_dying_cpu);
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if (ret)
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return -EINVAL;
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return 0;
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rollback:
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for_each_possible_cpu(cpu_rollback) {
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if (cpu_rollback == cpu)
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break;
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to = per_cpu_ptr(&csky_to, cpu_rollback);
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timer_of_cleanup(to);
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}
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return -EINVAL;
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}
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TIMER_OF_DECLARE(csky_mptimer, "csky,mptimer", csky_mptimer_init);
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