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alistair23-linux/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
Thomas Petazzoni d7d5a43c0d ARM: mvebu: fix overlap of Crypto SRAM with PCIe memory window 
When the Crypto SRAM mappings were added to the Device Tree files
describing the Armada XP boards in commit c466d997bb ("ARM: mvebu:
define crypto SRAM ranges for all armada-xp boards"), the fact that
those mappings were overlaping with the PCIe memory aperture was
overlooked. Due to this, we currently have for all Armada XP platforms
a situation that looks like this:

Memory mapping on Armada XP boards with internal registers at
0xf1000000:

 - 0x00000000 -> 0xf0000000	3.75G 	RAM
 - 0xf0000000 -> 0xf1000000	16M	NOR flashes (AXP GP / AXP DB)
 - 0xf1000000 -> 0xf1100000	1M	internal registers
 - 0xf8000000 -> 0xffe0000	126M	PCIe memory aperture
 - 0xf8100000 -> 0xf8110000	64KB	Crypto SRAM #0	=> OVERLAPS WITH PCIE !
 - 0xf8110000 -> 0xf8120000	64KB	Crypto SRAM #1	=> OVERLAPS WITH PCIE !
 - 0xffe00000 -> 0xfff00000	1M	PCIe I/O aperture
 - 0xfff0000  -> 0xffffffff	1M	BootROM

The overlap means that when PCIe devices are added, depending on their
memory window needs, they might or might not be mapped into the
physical address space. Indeed, they will not be mapped if the area
allocated in the PCIe memory aperture by the PCI core overlaps with
one of the Crypto SRAM. Typically, a Intel IGB PCIe NIC that needs 8MB
of PCIe memory will see its PCIe memory window allocated from
0xf80000000 for 8MB, which overlaps with the Crypto SRAM windows. Due
to this, the PCIe window is not created, and any attempt to access the
PCIe window makes the kernel explode:

[    3.302213] igb: Copyright (c) 2007-2014 Intel Corporation.
[    3.307841] pci 0000:00:09.0: enabling device (0140 -> 0143)
[    3.313539] mvebu_mbus: cannot add window '4:f8', conflicts with another window
[    3.320870] mvebu-pcie soc:pcie-controller: Could not create MBus window at [mem 0xf8000000-0xf87fffff]: -22
[    3.330811] Unhandled fault: external abort on non-linefetch (0x1008) at 0xf08c0018

This problem does not occur on Armada 370 boards, because we use the
following memory mapping (for boards that have internal registers at
0xf1000000):

 - 0x00000000 -> 0xf0000000	3.75G 	RAM
 - 0xf0000000 -> 0xf1000000	16M	NOR flashes (AXP GP / AXP DB)
 - 0xf1000000 -> 0xf1100000	1M	internal registers
 - 0xf1100000 -> 0xf1110000	64KB	Crypto SRAM #0 => OK !
 - 0xf8000000 -> 0xffe0000	126M	PCIe memory
 - 0xffe00000 -> 0xfff00000	1M	PCIe I/O
 - 0xfff0000  -> 0xffffffff	1M	BootROM

Obviously, the solution is to align the location of the Crypto SRAM
mappings of Armada XP to be similar with the ones on Armada 370, i.e
have them between the "internal registers" area and the beginning of
the PCIe aperture.

However, we have a special case with the OpenBlocks AX3-4 platform,
which has a 128 MB NOR flash. Currently, this NOR flash is mapped from
0xf0000000 to 0xf8000000. This is possible because on OpenBlocks
AX3-4, the internal registers are not at 0xf1000000. And this explains
why the Crypto SRAM mappings were not configured at the same place on
Armada XP.

Hence, the solution is two-fold:

 (1) Move the NOR flash mapping on Armada XP OpenBlocks AX3-4 from
     0xe8000000 to 0xf0000000. This frees the 0xf0000000 ->
     0xf80000000 space.

 (2) Move the Crypto SRAM mappings on Armada XP to be similar to
     Armada 370 (except of course that Armada XP has two Crypto SRAM
     and not one).

After this patch, the memory mapping on Armada XP boards with
registers at 0xf1 is:

 - 0x00000000 -> 0xf0000000	3.75G 	RAM
 - 0xf0000000 -> 0xf1000000	16M	NOR flashes (AXP GP / AXP DB)
 - 0xf1000000 -> 0xf1100000	1M	internal registers
 - 0xf1100000 -> 0xf1110000	64KB	Crypto SRAM #0
 - 0xf1110000 -> 0xf1120000	64KB	Crypto SRAM #1
 - 0xf8000000 -> 0xffe0000	126M	PCIe memory
 - 0xffe00000 -> 0xfff00000	1M	PCIe I/O
 - 0xfff0000  -> 0xffffffff	1M	BootROM

And the memory mapping for the special case of the OpenBlocks AX3-4
(internal registers at 0xd0000000, NOR of 128 MB):

 - 0x00000000 -> 0xc0000000	3G 	RAM
 - 0xd0000000 -> 0xd1000000	1M	internal registers
 - 0xe800000  -> 0xf0000000	128M	NOR flash
 - 0xf1100000 -> 0xf1110000	64KB	Crypto SRAM #0
 - 0xf1110000 -> 0xf1120000	64KB	Crypto SRAM #1
 - 0xf8000000 -> 0xffe0000	126M	PCIe memory
 - 0xffe00000 -> 0xfff00000	1M	PCIe I/O
 - 0xfff0000  -> 0xffffffff	1M	BootROM

Fixes: c466d997bb ("ARM: mvebu: define crypto SRAM ranges for all armada-xp boards")
Reported-by: Phil Sutter <phil@nwl.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: <stable@vger.kernel.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-11 11:49:55 -08:00

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/*
* Device Tree file for NETGEAR ReadyNAS 2120
*
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-xp-mv78230.dtsi"
/ {
model = "NETGEAR ReadyNAS 2120";
compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0 0x00000000 0 0x80000000>; /* 2GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
pcie-controller {
status = "okay";
/* Connected to first Marvell 88SE9170 SATA controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to second Marvell 88SE9170 SATA controller */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Connected to Fresco Logic FL1009 USB 3.0 controller */
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
rtc@10300 {
status = "disabled";
};
i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
clock-frequency = <400000>;
status = "okay";
/* Controller for rear fan #1 of 3 (Protechnic
* MGT4012XB-O20, 8000RPM) near eSATA port */
g762_fan1: g762@3e {
compatible = "gmt,g762";
reg = <0x3e>;
clocks = <&g762_clk>; /* input clock */
fan_gear_mode = <0>;
fan_startv = <1>;
pwm_polarity = <0>;
};
/* Controller for rear (center) fan #2 of 3 */
g762_fan2: g762@48 {
compatible = "gmt,g762";
reg = <0x48>;
clocks = <&g762_clk>; /* input clock */
fan_gear_mode = <0>;
fan_startv = <1>;
pwm_polarity = <0>;
};
/* Controller for rear fan #3 of 3 */
g762_fan3: g762@49 {
compatible = "gmt,g762";
reg = <0x49>;
clocks = <&g762_clk>; /* input clock */
fan_gear_mode = <0>;
fan_startv = <1>;
pwm_polarity = <0>;
};
/* Temperature sensor */
g751: g751@4c {
compatible = "gmt,g751";
reg = <0x4c>;
};
isl12057: isl12057@68 {
compatible = "isil,isl12057";
reg = <0x68>;
wakeup-source;
};
};
serial@12000 {
status = "okay";
};
/* Front USB 2.0 port */
usb@50000 {
status = "okay";
};
mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
reg = <1>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* Two rear eSATA ports */
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
nand@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
/* Use Hardware BCH ECC */
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x180000>; /* 1.5MB */
read-only;
};
partition@180000 {
label = "u-boot-env";
reg = <0x180000 0x20000>; /* 128KB */
read-only;
};
partition@200000 {
label = "uImage";
reg = <0x0200000 0x600000>; /* 6MB */
};
partition@800000 {
label = "minirootfs";
reg = <0x0800000 0x400000>; /* 4MB */
};
/* Last MB is for the BBT, i.e. not writable */
partition@c00000 {
label = "ubifs";
reg = <0x0c00000 0x7400000>; /* 116MB */
};
};
};
};
clocks {
g762_clk: g762-oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin
&sata3_led_pin &sata4_led_pin>;
pinctrl-names = "default";
red-sata1-led {
label = "rn2120:red:sata1";
gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red-sata2-led {
label = "rn2120:red:sata2";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red-sata3-led {
label = "rn2120:red:sata3";
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red-sata4-led {
label = "rn2120:red:sata4";
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red-err-led {
label = "rn2120:red:err";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&power_button_pin &reset_button_pin>;
pinctrl-names = "default";
power-button {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
};
reset-button {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
pinctrl-0 = <&poweroff>;
pinctrl-names = "default";
gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
poweroff: poweroff {
marvell,pins = "mpp42";
marvell,function = "gpio";
};
power_button_pin: power-button-pin {
marvell,pins = "mpp27";
marvell,function = "gpio";
};
reset_button_pin: reset-button-pin {
marvell,pins = "mpp41";
marvell,function = "gpio";
};
sata1_led_pin: sata1-led-pin {
marvell,pins = "mpp31";
marvell,function = "gpio";
};
sata2_led_pin: sata2-led-pin {
marvell,pins = "mpp40";
marvell,function = "gpio";
};
sata3_led_pin: sata3-led-pin {
marvell,pins = "mpp44";
marvell,function = "gpio";
};
sata4_led_pin: sata4-led-pin {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
sata1_power_pin: sata1-power-pin {
marvell,pins = "mpp24";
marvell,function = "gpio";
};
sata2_power_pin: sata2-power-pin {
marvell,pins = "mpp25";
marvell,function = "gpio";
};
sata3_power_pin: sata3-power-pin {
marvell,pins = "mpp26";
marvell,function = "gpio";
};
sata4_power_pin: sata4-power-pin {
marvell,pins = "mpp28";
marvell,function = "gpio";
};
sata1_pres_pin: sata1-pres-pin {
marvell,pins = "mpp32";
marvell,function = "gpio";
};
sata2_pres_pin: sata2-pres-pin {
marvell,pins = "mpp33";
marvell,function = "gpio";
};
sata3_pres_pin: sata3-pres-pin {
marvell,pins = "mpp34";
marvell,function = "gpio";
};
sata4_pres_pin: sata4-pres-pin {
marvell,pins = "mpp35";
marvell,function = "gpio";
};
err_led_pin: err-led-pin {
marvell,pins = "mpp45";
marvell,function = "gpio";
};
};
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