e537ecd7ef
So far, KVM was getting in the way of kexec on 32bit (and the arm64 kexec hackers couldn't be bothered to fix it on 32bit...). With simpler page tables, tearing KVM down becomes very easy, so let's just do it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
136 lines
3.6 KiB
ArmAsm
136 lines
3.6 KiB
ArmAsm
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/unified.h>
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#include <asm/asm-offsets.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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/********************************************************************
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* Hypervisor initialization
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* - should be called with:
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* r0 = top of Hyp stack (kernel VA)
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* r1 = pointer to hyp vectors
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* r2,r3 = Hypervisor pgd pointer
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*
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* The init scenario is:
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* - We jump in HYP with 3 parameters: runtime HYP pgd, runtime stack,
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* runtime vectors
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* - Invalidate TLBs
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* - Set stack and vectors
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* - Setup the page tables
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* - Enable the MMU
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* - Profit! (or eret, if you only care about the code).
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*/
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.text
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.pushsection .hyp.idmap.text,"ax"
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.align 5
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__kvm_hyp_init:
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.globl __kvm_hyp_init
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@ Hyp-mode exception vector
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W(b) .
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W(b) .
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W(b) .
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W(b) .
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W(b) .
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W(b) __do_hyp_init
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W(b) .
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W(b) .
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__do_hyp_init:
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@ Set stack pointer
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mov sp, r0
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@ Set HVBAR to point to the HYP vectors
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mcr p15, 4, r1, c12, c0, 0 @ HVBAR
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@ Set the HTTBR to point to the hypervisor PGD pointer passed
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mcrr p15, 4, rr_lo_hi(r2, r3), c2
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@ Set the HTCR and VTCR to the same shareability and cacheability
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@ settings as the non-secure TTBCR and with T0SZ == 0.
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mrc p15, 4, r0, c2, c0, 2 @ HTCR
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ldr r2, =HTCR_MASK
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bic r0, r0, r2
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mrc p15, 0, r1, c2, c0, 2 @ TTBCR
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and r1, r1, #(HTCR_MASK & ~TTBCR_T0SZ)
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orr r0, r0, r1
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mcr p15, 4, r0, c2, c0, 2 @ HTCR
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@ Use the same memory attributes for hyp. accesses as the kernel
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@ (copy MAIRx ro HMAIRx).
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mrc p15, 0, r0, c10, c2, 0
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mcr p15, 4, r0, c10, c2, 0
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mrc p15, 0, r0, c10, c2, 1
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mcr p15, 4, r0, c10, c2, 1
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@ Invalidate the stale TLBs from Bootloader
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mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH
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dsb ish
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@ Set the HSCTLR to:
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@ - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
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@ - Endianness: Kernel config
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@ - Fast Interrupt Features: Kernel config
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@ - Write permission implies XN: disabled
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@ - Instruction cache: enabled
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@ - Data/Unified cache: enabled
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@ - Memory alignment checks: enabled
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@ - MMU: enabled (this code must be run from an identity mapping)
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mrc p15, 4, r0, c1, c0, 0 @ HSCR
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ldr r2, =HSCTLR_MASK
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bic r0, r0, r2
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mrc p15, 0, r1, c1, c0, 0 @ SCTLR
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ldr r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
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and r1, r1, r2
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ARM( ldr r2, =(HSCTLR_M | HSCTLR_A) )
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THUMB( ldr r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE) )
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orr r1, r1, r2
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orr r0, r0, r1
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mcr p15, 4, r0, c1, c0, 0 @ HSCR
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isb
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eret
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@ r0 : stub vectors address
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ENTRY(__kvm_hyp_reset)
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/* We're now in idmap, disable MMU */
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mrc p15, 4, r1, c1, c0, 0 @ HSCTLR
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ldr r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I)
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bic r1, r1, r2
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mcr p15, 4, r1, c1, c0, 0 @ HSCTLR
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/* Install stub vectors */
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mcr p15, 4, r0, c12, c0, 0 @ HVBAR
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isb
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eret
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ENDPROC(__kvm_hyp_reset)
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.ltorg
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.globl __kvm_hyp_init_end
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__kvm_hyp_init_end:
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.popsection
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