1579c7b9fe
In order to save power the DDR pins should be put into high impedance when in suspend to RAM. This requires manually requesting self refresh (rather than using the automatic mode implemented by the CCM / ESDCTL), followed by reconfiguring the IOMUXC. Of course the code to do this cannot itself run from DDR so the code is copied to and executed from internal memory. In my tests using a custom i.MX53 board with LPDDR2 RAM this reduced the suspend power consumption from 200mW to 60mW. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
140 lines
3.4 KiB
ArmAsm
140 lines
3.4 KiB
ArmAsm
/*
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* Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/linkage.h>
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#define M4IF_MCR0_OFFSET (0x008C)
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#define M4IF_MCR0_FDVFS (0x1 << 11)
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#define M4IF_MCR0_FDVACK (0x1 << 27)
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.align 3
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/*
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* ==================== low level suspend ====================
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*
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* On entry
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* r0: pm_info structure address;
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*
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* suspend ocram space layout:
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* ======================== high address ======================
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* .
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* .
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* .
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* ^
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* ^
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* ^
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* imx53_suspend code
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* PM_INFO structure(imx53_suspend_info)
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* ======================== low address =======================
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*/
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/* Offsets of members of struct imx53_suspend_info */
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#define SUSPEND_INFO_MX53_M4IF_V_OFFSET 0x0
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#define SUSPEND_INFO_MX53_IOMUXC_V_OFFSET 0x4
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#define SUSPEND_INFO_MX53_IO_COUNT_OFFSET 0x8
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#define SUSPEND_INFO_MX53_IO_STATE_OFFSET 0xc
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ENTRY(imx53_suspend)
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stmfd sp!, {r4,r5,r6,r7}
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/* Save pad config */
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ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET]
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cmp r1, #0
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beq skip_pad_conf_1
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add r2, r0, #SUSPEND_INFO_MX53_IO_STATE_OFFSET
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ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET]
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1:
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ldr r5, [r2], #12 /* IOMUXC register offset */
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ldr r6, [r3, r5] /* current value */
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str r6, [r2], #4 /* save area */
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subs r1, r1, #1
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bne 1b
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skip_pad_conf_1:
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/* Set FDVFS bit of M4IF_MCR0 to request DDR to enter self-refresh */
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ldr r1, [r0, #SUSPEND_INFO_MX53_M4IF_V_OFFSET]
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ldr r2,[r1, #M4IF_MCR0_OFFSET]
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orr r2, r2, #M4IF_MCR0_FDVFS
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str r2,[r1, #M4IF_MCR0_OFFSET]
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/* Poll FDVACK bit of M4IF_MCR to wait for DDR to enter self-refresh */
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wait_sr_ack:
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ldr r2,[r1, #M4IF_MCR0_OFFSET]
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ands r2, r2, #M4IF_MCR0_FDVACK
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beq wait_sr_ack
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/* Set pad config */
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ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET]
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cmp r1, #0
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beq skip_pad_conf_2
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add r2, r0, #SUSPEND_INFO_MX53_IO_STATE_OFFSET
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ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET]
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2:
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ldr r5, [r2], #4 /* IOMUXC register offset */
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ldr r6, [r2], #4 /* clear */
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ldr r7, [r3, r5]
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bic r7, r7, r6
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ldr r6, [r2], #8 /* set */
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orr r7, r7, r6
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str r7, [r3, r5]
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subs r1, r1, #1
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bne 2b
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skip_pad_conf_2:
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/* Zzz, enter stop mode */
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wfi
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nop
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nop
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nop
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nop
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/* Restore pad config */
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ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET]
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cmp r1, #0
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beq skip_pad_conf_3
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add r2, r0, #SUSPEND_INFO_MX53_IO_STATE_OFFSET
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ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET]
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3:
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ldr r5, [r2], #12 /* IOMUXC register offset */
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ldr r6, [r2], #4 /* saved value */
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str r6, [r3, r5]
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subs r1, r1, #1
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bne 3b
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skip_pad_conf_3:
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/* Clear FDVFS bit of M4IF_MCR0 to request DDR to exit self-refresh */
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ldr r1, [r0, #SUSPEND_INFO_MX53_M4IF_V_OFFSET]
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ldr r2,[r1, #M4IF_MCR0_OFFSET]
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bic r2, r2, #M4IF_MCR0_FDVFS
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str r2,[r1, #M4IF_MCR0_OFFSET]
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/* Poll FDVACK bit of M4IF_MCR to wait for DDR to exit self-refresh */
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wait_ar_ack:
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ldr r2,[r1, #M4IF_MCR0_OFFSET]
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ands r2, r2, #M4IF_MCR0_FDVACK
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bne wait_ar_ack
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/* Restore registers */
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ldmfd sp!, {r4,r5,r6,r7}
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mov pc, lr
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ENDPROC(imx53_suspend)
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ENTRY(imx53_suspend_sz)
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.word . - imx53_suspend
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