f81309067f
The existing memory barrier macro causes a significant amount of code to be inserted inline at every call site. For example, in gpio_set_irq_type(), we have this for mb(): c0344c08: f57ff04e dsb st c0344c0c: e59f8190 ldr r8, [pc, #400] ; c0344da4 <gpio_set_irq_type+0x230> c0344c10: e3590004 cmp r9, #4 c0344c14: e5983014 ldr r3, [r8, #20] c0344c18: 0a000054 beq c0344d70 <gpio_set_irq_type+0x1fc> c0344c1c: e3530000 cmp r3, #0 c0344c20: 0a000004 beq c0344c38 <gpio_set_irq_type+0xc4> c0344c24: e50b2030 str r2, [fp, #-48] ; 0xffffffd0 c0344c28: e50bc034 str ip, [fp, #-52] ; 0xffffffcc c0344c2c: e12fff33 blx r3 c0344c30: e51bc034 ldr ip, [fp, #-52] ; 0xffffffcc c0344c34: e51b2030 ldr r2, [fp, #-48] ; 0xffffffd0 c0344c38: e5963004 ldr r3, [r6, #4] Moving the outer_cache_sync() call out of line reduces the impact of the barrier: c0344968: f57ff04e dsb st c034496c: e35a0004 cmp sl, #4 c0344970: e50b2030 str r2, [fp, #-48] ; 0xffffffd0 c0344974: 0a000044 beq c0344a8c <gpio_set_irq_type+0x1b8> c0344978: ebf363dd bl c001d8f4 <arm_heavy_mb> c034497c: e5953004 ldr r3, [r5, #4] This should reduce the cache footprint of this code. Overall, this results in a reduction of around 20K in the kernel size: text data bss dec hex filename 10773970 667392 10369656 21811018 14ccf4a ../build/imx6/vmlinux-old 10754219 667392 10369656 21791267 14c8223 ../build/imx6/vmlinux-new Another advantage to this approach is that we can finally resolve the issue of SoCs which have their own memory barrier requirements within multiplatform kernels (such as OMAP.) Here, the bus interconnects need additional handling to ensure that writes become visible in the correct order (eg, between dma_map() operations, writes to DMA coherent memory, and MMIO accesses.) Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
155 lines
3.4 KiB
C
155 lines
3.4 KiB
C
/*
|
|
* power management entry for CSR SiRFprimaII
|
|
*
|
|
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
|
|
*
|
|
* Licensed under GPLv2 or later.
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/suspend.h>
|
|
#include <linux/slab.h>
|
|
#include <linux/export.h>
|
|
#include <linux/of.h>
|
|
#include <linux/of_address.h>
|
|
#include <linux/of_device.h>
|
|
#include <linux/of_platform.h>
|
|
#include <linux/io.h>
|
|
#include <linux/rtc/sirfsoc_rtciobrg.h>
|
|
#include <asm/outercache.h>
|
|
#include <asm/suspend.h>
|
|
#include <asm/hardware/cache-l2x0.h>
|
|
|
|
#include "pm.h"
|
|
|
|
/*
|
|
* suspend asm codes will access these to make DRAM become self-refresh and
|
|
* system sleep
|
|
*/
|
|
u32 sirfsoc_pwrc_base;
|
|
void __iomem *sirfsoc_memc_base;
|
|
|
|
static void sirfsoc_set_wakeup_source(void)
|
|
{
|
|
u32 pwr_trigger_en_reg;
|
|
pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
|
|
SIRFSOC_PWRC_TRIGGER_EN);
|
|
#define X_ON_KEY_B (1 << 0)
|
|
#define RTC_ALARM0_B (1 << 2)
|
|
#define RTC_ALARM1_B (1 << 3)
|
|
sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B |
|
|
RTC_ALARM0_B | RTC_ALARM1_B,
|
|
sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
|
|
}
|
|
|
|
static void sirfsoc_set_sleep_mode(u32 mode)
|
|
{
|
|
u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
|
|
SIRFSOC_PWRC_PDN_CTRL);
|
|
sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1);
|
|
sleep_mode |= mode << 1;
|
|
sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base +
|
|
SIRFSOC_PWRC_PDN_CTRL);
|
|
}
|
|
|
|
static int sirfsoc_pre_suspend_power_off(void)
|
|
{
|
|
u32 wakeup_entry = virt_to_phys(cpu_resume);
|
|
|
|
sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
|
|
SIRFSOC_PWRC_SCRATCH_PAD1);
|
|
|
|
sirfsoc_set_wakeup_source();
|
|
|
|
sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sirfsoc_pm_enter(suspend_state_t state)
|
|
{
|
|
switch (state) {
|
|
case PM_SUSPEND_MEM:
|
|
sirfsoc_pre_suspend_power_off();
|
|
|
|
outer_disable();
|
|
/* go zzz */
|
|
cpu_suspend(0, sirfsoc_finish_suspend);
|
|
outer_resume();
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_suspend_ops sirfsoc_pm_ops = {
|
|
.enter = sirfsoc_pm_enter,
|
|
.valid = suspend_valid_only_mem,
|
|
};
|
|
|
|
static const struct of_device_id pwrc_ids[] = {
|
|
{ .compatible = "sirf,prima2-pwrc" },
|
|
{}
|
|
};
|
|
|
|
static int __init sirfsoc_of_pwrc_init(void)
|
|
{
|
|
struct device_node *np;
|
|
|
|
np = of_find_matching_node(NULL, pwrc_ids);
|
|
if (!np) {
|
|
pr_err("unable to find compatible sirf pwrc node in dtb\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
/*
|
|
* pwrc behind rtciobrg is not located in memory space
|
|
* though the property is named reg. reg only means base
|
|
* offset for pwrc. then of_iomap is not suitable here.
|
|
*/
|
|
if (of_property_read_u32(np, "reg", &sirfsoc_pwrc_base))
|
|
panic("unable to find base address of pwrc node in dtb\n");
|
|
|
|
of_node_put(np);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id memc_ids[] = {
|
|
{ .compatible = "sirf,prima2-memc" },
|
|
{}
|
|
};
|
|
|
|
static int sirfsoc_memc_probe(struct platform_device *op)
|
|
{
|
|
struct device_node *np = op->dev.of_node;
|
|
|
|
sirfsoc_memc_base = of_iomap(np, 0);
|
|
if (!sirfsoc_memc_base)
|
|
panic("unable to map memc registers\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sirfsoc_memc_driver = {
|
|
.probe = sirfsoc_memc_probe,
|
|
.driver = {
|
|
.name = "sirfsoc-memc",
|
|
.of_match_table = memc_ids,
|
|
},
|
|
};
|
|
|
|
static int __init sirfsoc_memc_init(void)
|
|
{
|
|
return platform_driver_register(&sirfsoc_memc_driver);
|
|
}
|
|
|
|
int __init sirfsoc_pm_init(void)
|
|
{
|
|
sirfsoc_of_pwrc_init();
|
|
sirfsoc_memc_init();
|
|
suspend_set_ops(&sirfsoc_pm_ops);
|
|
return 0;
|
|
}
|