f6361c6b38
The restart-handler series from Guenter Roeck got accepted recently and implements among other things also the restart handler in the samsung watchdog driver and where applicable in the clock drivers. So there is no need for having the restart callbacks in s3c24xx boards anymore. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
434 lines
10 KiB
C
434 lines
10 KiB
C
/* linux/arch/arm/mach-s3c2440/mach-anubis.c
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*
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* Copyright 2003-2009 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <linux/platform_device.h>
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#include <linux/ata_platform.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/sm501.h>
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#include <linux/sm501-regs.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-lcd.h>
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#include <mach/gpio-samsung.h>
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#include <linux/platform_data/mtd-nand-s3c2410.h>
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#include <linux/platform_data/i2c-s3c2410.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <net/ax88796.h>
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#include <plat/devs.h>
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#include <plat/cpu.h>
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#include <linux/platform_data/asoc-s3c24xx_simtec.h>
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#include <plat/samsung-time.h>
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#include "anubis.h"
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#include "common.h"
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#include "simtec.h"
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#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
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static struct map_desc anubis_iodesc[] __initdata = {
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/* ISA IO areas */
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{
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.virtual = (u32)S3C24XX_VA_ISA_BYTE,
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.pfn = __phys_to_pfn(0x0),
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.length = SZ_4M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = __phys_to_pfn(0x0),
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.length = SZ_4M,
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.type = MT_DEVICE,
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},
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/* we could possibly compress the next set down into a set of smaller tables
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* pagetables, but that would mean using an L2 section, and it still means
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* we cannot actually feed the same register to an LDR due to 16K spacing
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*/
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/* CPLD control registers */
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{
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.virtual = (u32)ANUBIS_VA_CTRL1,
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.pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)ANUBIS_VA_IDREG,
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.pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
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#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
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#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
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static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
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},
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[1] = {
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.hwport = 2,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
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},
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};
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/* NAND Flash on Anubis board */
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static int external_map[] = { 2 };
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static int chip0_map[] = { 0 };
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static int chip1_map[] = { 1 };
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static struct mtd_partition __initdata anubis_default_nand_part[] = {
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[0] = {
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.name = "Boot Agent",
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.size = SZ_16K,
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.offset = 0,
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},
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[1] = {
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.name = "/boot",
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.size = SZ_4M - SZ_16K,
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.offset = SZ_16K,
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},
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[2] = {
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.name = "user1",
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.offset = SZ_4M,
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.size = SZ_32M - SZ_4M,
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},
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[3] = {
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.name = "user2",
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.offset = SZ_32M,
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.size = MTDPART_SIZ_FULL,
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}
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};
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static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
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[0] = {
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.name = "Boot Agent",
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.size = SZ_128K,
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.offset = 0,
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},
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[1] = {
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.name = "/boot",
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.size = SZ_4M - SZ_128K,
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.offset = SZ_128K,
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},
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[2] = {
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.name = "user1",
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.offset = SZ_4M,
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.size = SZ_32M - SZ_4M,
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},
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[3] = {
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.name = "user2",
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.offset = SZ_32M,
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.size = MTDPART_SIZ_FULL,
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}
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};
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/* the Anubis has 3 selectable slots for nand-flash, the two
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* on-board chip areas, as well as the external slot.
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*
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* Note, there is no current hot-plug support for the External
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* socket.
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*/
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static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
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[1] = {
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.name = "External",
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.nr_chips = 1,
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.nr_map = external_map,
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.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
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.partitions = anubis_default_nand_part,
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},
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[0] = {
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.name = "chip0",
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.nr_chips = 1,
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.nr_map = chip0_map,
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.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
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.partitions = anubis_default_nand_part,
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},
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[2] = {
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.name = "chip1",
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.nr_chips = 1,
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.nr_map = chip1_map,
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.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
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.partitions = anubis_default_nand_part,
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},
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};
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static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
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{
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unsigned int tmp;
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slot = set->nr_map[slot] & 3;
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pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
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slot, set, set->nr_map);
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tmp = __raw_readb(ANUBIS_VA_CTRL1);
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tmp &= ~ANUBIS_CTRL1_NANDSEL;
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tmp |= slot;
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pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
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__raw_writeb(tmp, ANUBIS_VA_CTRL1);
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}
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static struct s3c2410_platform_nand __initdata anubis_nand_info = {
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.tacls = 25,
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.twrph0 = 55,
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.twrph1 = 40,
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.nr_sets = ARRAY_SIZE(anubis_nand_sets),
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.sets = anubis_nand_sets,
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.select_chip = anubis_nand_select,
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};
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/* IDE channels */
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static struct pata_platform_info anubis_ide_platdata = {
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.ioport_shift = 5,
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};
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static struct resource anubis_ide0_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
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[2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
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[3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
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};
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static struct platform_device anubis_device_ide0 = {
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.name = "pata_platform",
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.id = 0,
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.num_resources = ARRAY_SIZE(anubis_ide0_resource),
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.resource = anubis_ide0_resource,
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.dev = {
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.platform_data = &anubis_ide_platdata,
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.coherent_dma_mask = ~0,
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},
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};
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static struct resource anubis_ide1_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
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[1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
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[2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
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};
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static struct platform_device anubis_device_ide1 = {
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.name = "pata_platform",
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.id = 1,
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.num_resources = ARRAY_SIZE(anubis_ide1_resource),
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.resource = anubis_ide1_resource,
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.dev = {
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.platform_data = &anubis_ide_platdata,
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.coherent_dma_mask = ~0,
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},
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};
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/* Asix AX88796 10/100 ethernet controller */
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static struct ax_plat_data anubis_asix_platdata = {
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.flags = AXFLG_MAC_FROMDEV,
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.wordlength = 2,
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.dcr_val = 0x48,
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.rcr_val = 0x40,
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};
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static struct resource anubis_asix_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
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[1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
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};
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static struct platform_device anubis_device_asix = {
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.name = "ax88796",
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.id = 0,
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.num_resources = ARRAY_SIZE(anubis_asix_resource),
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.resource = anubis_asix_resource,
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.dev = {
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.platform_data = &anubis_asix_platdata,
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}
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};
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/* SM501 */
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static struct resource anubis_sm501_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_CS2, SZ_8M),
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[1] = DEFINE_RES_MEM(S3C2410_CS2 + SZ_64M - SZ_2M, SZ_2M),
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[2] = DEFINE_RES_IRQ(IRQ_EINT0),
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};
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static struct sm501_initdata anubis_sm501_initdata = {
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.gpio_high = {
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.set = 0x3F000000, /* 24bit panel */
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.mask = 0x0,
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},
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.misc_timing = {
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.set = 0x010100, /* SDRAM timing */
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.mask = 0x1F1F00,
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},
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.misc_control = {
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.set = SM501_MISC_PNL_24BIT,
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.mask = 0,
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},
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.devices = SM501_USE_GPIO,
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/* set the SDRAM and bus clocks */
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.mclk = 72 * MHZ,
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.m1xclk = 144 * MHZ,
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};
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static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
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[0] = {
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.bus_num = 1,
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.pin_scl = 44,
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.pin_sda = 45,
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},
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[1] = {
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.bus_num = 2,
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.pin_scl = 40,
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.pin_sda = 41,
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},
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};
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static struct sm501_platdata anubis_sm501_platdata = {
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.init = &anubis_sm501_initdata,
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.gpio_base = -1,
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.gpio_i2c = anubis_sm501_gpio_i2c,
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.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
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};
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static struct platform_device anubis_device_sm501 = {
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.name = "sm501",
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.id = 0,
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.num_resources = ARRAY_SIZE(anubis_sm501_resource),
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.resource = anubis_sm501_resource,
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.dev = {
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.platform_data = &anubis_sm501_platdata,
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},
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};
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/* Standard Anubis devices */
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static struct platform_device *anubis_devices[] __initdata = {
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&s3c2410_device_dclk,
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&s3c_device_ohci,
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&s3c_device_wdt,
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&s3c_device_adc,
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&s3c_device_i2c0,
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&s3c_device_rtc,
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&s3c_device_nand,
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&anubis_device_ide0,
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&anubis_device_ide1,
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&anubis_device_asix,
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&anubis_device_sm501,
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};
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/* I2C devices. */
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static struct i2c_board_info anubis_i2c_devs[] __initdata = {
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{
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I2C_BOARD_INFO("tps65011", 0x48),
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.irq = IRQ_EINT20,
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}
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};
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/* Audio setup */
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static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
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.have_mic = 1,
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.have_lout = 1,
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.output_cdclk = 1,
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.use_mpllin = 1,
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.amp_gpio = S3C2410_GPB(2),
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.amp_gain[0] = S3C2410_GPD(10),
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.amp_gain[1] = S3C2410_GPD(11),
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};
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static void __init anubis_map_io(void)
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{
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s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
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s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
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samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
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/* check for the newer revision boards with large page nand */
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if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
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printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
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__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
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anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
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anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
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} else {
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/* ensure that the GPIO is setup */
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gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
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gpio_free(S3C2410_GPA(0));
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}
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}
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static void __init anubis_init_time(void)
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{
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s3c2440_init_clocks(12000000);
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samsung_timer_init();
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}
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static void __init anubis_init(void)
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{
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s3c_i2c0_set_platdata(NULL);
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s3c_nand_set_platdata(&anubis_nand_info);
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simtec_audio_add(NULL, false, &anubis_audio);
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platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
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i2c_register_board_info(0, anubis_i2c_devs,
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ARRAY_SIZE(anubis_i2c_devs));
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}
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MACHINE_START(ANUBIS, "Simtec-Anubis")
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/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
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.atag_offset = 0x100,
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.map_io = anubis_map_io,
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.init_machine = anubis_init,
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.init_irq = s3c2440_init_irq,
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.init_time = anubis_init_time,
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MACHINE_END
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