![Simon Horman](/assets/img/avatar_default.png)
The reason for this is to ensure that CMT is probed earlier than with its previous initcall level, module init. This came up as a problem with using kzm9g-reference which does not make use of early timers or devices. In that scenario initialisation of SDHI and MMCIF both stall on msleep() calls due to the absence of a initialised clock source. Boot tested on: armadillo800eva, mackerel and kzm9g Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
847 lines
20 KiB
C
847 lines
20 KiB
C
/*
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* SuperH Timer Support - CMT
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*
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* Copyright (C) 2008 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/sh_timer.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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struct sh_cmt_priv {
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void __iomem *mapbase;
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struct clk *clk;
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unsigned long width; /* 16 or 32 bit version of hardware block */
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unsigned long overflow_bit;
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unsigned long clear_bits;
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struct irqaction irqaction;
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struct platform_device *pdev;
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unsigned long flags;
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unsigned long match_value;
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unsigned long next_match_value;
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unsigned long max_match_value;
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unsigned long rate;
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raw_spinlock_t lock;
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struct clock_event_device ced;
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struct clocksource cs;
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unsigned long total_cycles;
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bool cs_enabled;
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/* callbacks for CMSTR and CMCSR access */
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unsigned long (*read_control)(void __iomem *base, unsigned long offs);
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void (*write_control)(void __iomem *base, unsigned long offs,
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unsigned long value);
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/* callbacks for CMCNT and CMCOR access */
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unsigned long (*read_count)(void __iomem *base, unsigned long offs);
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void (*write_count)(void __iomem *base, unsigned long offs,
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unsigned long value);
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};
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/* Examples of supported CMT timer register layouts and I/O access widths:
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*
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* "16-bit counter and 16-bit control" as found on sh7263:
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* CMSTR 0xfffec000 16-bit
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* CMCSR 0xfffec002 16-bit
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* CMCNT 0xfffec004 16-bit
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* CMCOR 0xfffec006 16-bit
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*
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* "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740:
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* CMSTR 0xffca0000 16-bit
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* CMCSR 0xffca0060 16-bit
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* CMCNT 0xffca0064 32-bit
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* CMCOR 0xffca0068 32-bit
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*/
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static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
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{
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return ioread16(base + (offs << 1));
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}
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static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
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{
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return ioread32(base + (offs << 2));
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}
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static void sh_cmt_write16(void __iomem *base, unsigned long offs,
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unsigned long value)
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{
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iowrite16(value, base + (offs << 1));
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}
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static void sh_cmt_write32(void __iomem *base, unsigned long offs,
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unsigned long value)
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{
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iowrite32(value, base + (offs << 2));
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}
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#define CMCSR 0 /* channel register */
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#define CMCNT 1 /* channel register */
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#define CMCOR 2 /* channel register */
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static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_priv *p)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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return p->read_control(p->mapbase - cfg->channel_offset, 0);
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}
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static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_priv *p)
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{
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return p->read_control(p->mapbase, CMCSR);
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}
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static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_priv *p)
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{
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return p->read_count(p->mapbase, CMCNT);
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}
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static inline void sh_cmt_write_cmstr(struct sh_cmt_priv *p,
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unsigned long value)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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p->write_control(p->mapbase - cfg->channel_offset, 0, value);
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}
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static inline void sh_cmt_write_cmcsr(struct sh_cmt_priv *p,
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unsigned long value)
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{
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p->write_control(p->mapbase, CMCSR, value);
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}
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static inline void sh_cmt_write_cmcnt(struct sh_cmt_priv *p,
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unsigned long value)
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{
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p->write_count(p->mapbase, CMCNT, value);
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}
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static inline void sh_cmt_write_cmcor(struct sh_cmt_priv *p,
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unsigned long value)
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{
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p->write_count(p->mapbase, CMCOR, value);
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}
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static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
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int *has_wrapped)
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{
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unsigned long v1, v2, v3;
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int o1, o2;
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o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit;
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/* Make sure the timer value is stable. Stolen from acpi_pm.c */
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do {
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o2 = o1;
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v1 = sh_cmt_read_cmcnt(p);
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v2 = sh_cmt_read_cmcnt(p);
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v3 = sh_cmt_read_cmcnt(p);
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o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit;
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} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
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|| (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
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*has_wrapped = o1;
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return v2;
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}
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static DEFINE_RAW_SPINLOCK(sh_cmt_lock);
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static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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raw_spin_lock_irqsave(&sh_cmt_lock, flags);
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value = sh_cmt_read_cmstr(p);
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if (start)
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value |= 1 << cfg->timer_bit;
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else
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value &= ~(1 << cfg->timer_bit);
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sh_cmt_write_cmstr(p, value);
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raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
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}
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static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
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{
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int k, ret;
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pm_runtime_get_sync(&p->pdev->dev);
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dev_pm_syscore_device(&p->pdev->dev, true);
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/* enable clock */
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ret = clk_enable(p->clk);
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if (ret) {
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dev_err(&p->pdev->dev, "cannot enable clock\n");
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goto err0;
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}
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/* make sure channel is disabled */
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sh_cmt_start_stop_ch(p, 0);
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/* configure channel, periodic mode and maximum timeout */
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if (p->width == 16) {
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*rate = clk_get_rate(p->clk) / 512;
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sh_cmt_write_cmcsr(p, 0x43);
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} else {
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*rate = clk_get_rate(p->clk) / 8;
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sh_cmt_write_cmcsr(p, 0x01a4);
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}
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sh_cmt_write_cmcor(p, 0xffffffff);
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sh_cmt_write_cmcnt(p, 0);
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/*
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* According to the sh73a0 user's manual, as CMCNT can be operated
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* only by the RCLK (Pseudo 32 KHz), there's one restriction on
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* modifying CMCNT register; two RCLK cycles are necessary before
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* this register is either read or any modification of the value
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* it holds is reflected in the LSI's actual operation.
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*
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* While at it, we're supposed to clear out the CMCNT as of this
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* moment, so make sure it's processed properly here. This will
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* take RCLKx2 at maximum.
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*/
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for (k = 0; k < 100; k++) {
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if (!sh_cmt_read_cmcnt(p))
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break;
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udelay(1);
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}
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if (sh_cmt_read_cmcnt(p)) {
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dev_err(&p->pdev->dev, "cannot clear CMCNT\n");
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ret = -ETIMEDOUT;
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goto err1;
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}
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/* enable channel */
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sh_cmt_start_stop_ch(p, 1);
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return 0;
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err1:
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/* stop clock */
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clk_disable(p->clk);
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err0:
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return ret;
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}
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static void sh_cmt_disable(struct sh_cmt_priv *p)
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{
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/* disable channel */
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sh_cmt_start_stop_ch(p, 0);
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/* disable interrupts in CMT block */
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sh_cmt_write_cmcsr(p, 0);
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/* stop clock */
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clk_disable(p->clk);
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dev_pm_syscore_device(&p->pdev->dev, false);
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pm_runtime_put(&p->pdev->dev);
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}
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/* private flags */
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#define FLAG_CLOCKEVENT (1 << 0)
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#define FLAG_CLOCKSOURCE (1 << 1)
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#define FLAG_REPROGRAM (1 << 2)
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#define FLAG_SKIPEVENT (1 << 3)
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#define FLAG_IRQCONTEXT (1 << 4)
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static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
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int absolute)
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{
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unsigned long new_match;
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unsigned long value = p->next_match_value;
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unsigned long delay = 0;
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unsigned long now = 0;
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int has_wrapped;
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now = sh_cmt_get_counter(p, &has_wrapped);
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p->flags |= FLAG_REPROGRAM; /* force reprogram */
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if (has_wrapped) {
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/* we're competing with the interrupt handler.
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* -> let the interrupt handler reprogram the timer.
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* -> interrupt number two handles the event.
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*/
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p->flags |= FLAG_SKIPEVENT;
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return;
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}
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if (absolute)
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now = 0;
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do {
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/* reprogram the timer hardware,
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* but don't save the new match value yet.
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*/
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new_match = now + value + delay;
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if (new_match > p->max_match_value)
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new_match = p->max_match_value;
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sh_cmt_write_cmcor(p, new_match);
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now = sh_cmt_get_counter(p, &has_wrapped);
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if (has_wrapped && (new_match > p->match_value)) {
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/* we are changing to a greater match value,
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* so this wrap must be caused by the counter
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* matching the old value.
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* -> first interrupt reprograms the timer.
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* -> interrupt number two handles the event.
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*/
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p->flags |= FLAG_SKIPEVENT;
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break;
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}
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if (has_wrapped) {
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/* we are changing to a smaller match value,
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* so the wrap must be caused by the counter
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* matching the new value.
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* -> save programmed match value.
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* -> let isr handle the event.
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*/
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p->match_value = new_match;
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break;
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}
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/* be safe: verify hardware settings */
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if (now < new_match) {
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/* timer value is below match value, all good.
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* this makes sure we won't miss any match events.
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* -> save programmed match value.
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* -> let isr handle the event.
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*/
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p->match_value = new_match;
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break;
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}
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/* the counter has reached a value greater
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* than our new match value. and since the
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* has_wrapped flag isn't set we must have
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* programmed a too close event.
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* -> increase delay and retry.
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*/
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if (delay)
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delay <<= 1;
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else
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delay = 1;
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if (!delay)
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dev_warn(&p->pdev->dev, "too long delay\n");
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} while (delay);
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}
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static void __sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
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{
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if (delta > p->max_match_value)
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dev_warn(&p->pdev->dev, "delta out of range\n");
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p->next_match_value = delta;
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sh_cmt_clock_event_program_verify(p, 0);
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}
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static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&p->lock, flags);
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__sh_cmt_set_next(p, delta);
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raw_spin_unlock_irqrestore(&p->lock, flags);
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}
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static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
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{
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struct sh_cmt_priv *p = dev_id;
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/* clear flags */
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sh_cmt_write_cmcsr(p, sh_cmt_read_cmcsr(p) & p->clear_bits);
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/* update clock source counter to begin with if enabled
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* the wrap flag should be cleared by the timer specific
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* isr before we end up here.
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*/
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if (p->flags & FLAG_CLOCKSOURCE)
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p->total_cycles += p->match_value + 1;
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if (!(p->flags & FLAG_REPROGRAM))
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p->next_match_value = p->max_match_value;
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p->flags |= FLAG_IRQCONTEXT;
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if (p->flags & FLAG_CLOCKEVENT) {
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if (!(p->flags & FLAG_SKIPEVENT)) {
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if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
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p->next_match_value = p->max_match_value;
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p->flags |= FLAG_REPROGRAM;
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}
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p->ced.event_handler(&p->ced);
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}
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}
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p->flags &= ~FLAG_SKIPEVENT;
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if (p->flags & FLAG_REPROGRAM) {
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p->flags &= ~FLAG_REPROGRAM;
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sh_cmt_clock_event_program_verify(p, 1);
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if (p->flags & FLAG_CLOCKEVENT)
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if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
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|| (p->match_value == p->next_match_value))
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p->flags &= ~FLAG_REPROGRAM;
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}
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p->flags &= ~FLAG_IRQCONTEXT;
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return IRQ_HANDLED;
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}
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static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
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{
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int ret = 0;
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unsigned long flags;
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raw_spin_lock_irqsave(&p->lock, flags);
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if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
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ret = sh_cmt_enable(p, &p->rate);
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if (ret)
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goto out;
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p->flags |= flag;
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/* setup timeout if no clockevent */
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if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
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__sh_cmt_set_next(p, p->max_match_value);
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out:
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raw_spin_unlock_irqrestore(&p->lock, flags);
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return ret;
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}
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static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
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{
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unsigned long flags;
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unsigned long f;
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raw_spin_lock_irqsave(&p->lock, flags);
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f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
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p->flags &= ~flag;
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if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
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sh_cmt_disable(p);
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/* adjust the timeout to maximum if only clocksource left */
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if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
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__sh_cmt_set_next(p, p->max_match_value);
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raw_spin_unlock_irqrestore(&p->lock, flags);
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}
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static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
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{
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return container_of(cs, struct sh_cmt_priv, cs);
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}
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static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
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{
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struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
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unsigned long flags, raw;
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unsigned long value;
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int has_wrapped;
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raw_spin_lock_irqsave(&p->lock, flags);
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value = p->total_cycles;
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raw = sh_cmt_get_counter(p, &has_wrapped);
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if (unlikely(has_wrapped))
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raw += p->match_value + 1;
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raw_spin_unlock_irqrestore(&p->lock, flags);
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return value + raw;
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}
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static int sh_cmt_clocksource_enable(struct clocksource *cs)
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{
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int ret;
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struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
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WARN_ON(p->cs_enabled);
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p->total_cycles = 0;
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ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
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if (!ret) {
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__clocksource_updatefreq_hz(cs, p->rate);
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p->cs_enabled = true;
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}
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return ret;
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}
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static void sh_cmt_clocksource_disable(struct clocksource *cs)
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{
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struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
|
|
|
|
WARN_ON(!p->cs_enabled);
|
|
|
|
sh_cmt_stop(p, FLAG_CLOCKSOURCE);
|
|
p->cs_enabled = false;
|
|
}
|
|
|
|
static void sh_cmt_clocksource_suspend(struct clocksource *cs)
|
|
{
|
|
struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
|
|
|
|
sh_cmt_stop(p, FLAG_CLOCKSOURCE);
|
|
pm_genpd_syscore_poweroff(&p->pdev->dev);
|
|
}
|
|
|
|
static void sh_cmt_clocksource_resume(struct clocksource *cs)
|
|
{
|
|
struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
|
|
|
|
pm_genpd_syscore_poweron(&p->pdev->dev);
|
|
sh_cmt_start(p, FLAG_CLOCKSOURCE);
|
|
}
|
|
|
|
static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
|
|
char *name, unsigned long rating)
|
|
{
|
|
struct clocksource *cs = &p->cs;
|
|
|
|
cs->name = name;
|
|
cs->rating = rating;
|
|
cs->read = sh_cmt_clocksource_read;
|
|
cs->enable = sh_cmt_clocksource_enable;
|
|
cs->disable = sh_cmt_clocksource_disable;
|
|
cs->suspend = sh_cmt_clocksource_suspend;
|
|
cs->resume = sh_cmt_clocksource_resume;
|
|
cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
|
|
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
|
|
|
|
dev_info(&p->pdev->dev, "used as clock source\n");
|
|
|
|
/* Register with dummy 1 Hz value, gets updated in ->enable() */
|
|
clocksource_register_hz(cs, 1);
|
|
return 0;
|
|
}
|
|
|
|
static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
|
|
{
|
|
return container_of(ced, struct sh_cmt_priv, ced);
|
|
}
|
|
|
|
static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
|
|
{
|
|
struct clock_event_device *ced = &p->ced;
|
|
|
|
sh_cmt_start(p, FLAG_CLOCKEVENT);
|
|
|
|
/* TODO: calculate good shift from rate and counter bit width */
|
|
|
|
ced->shift = 32;
|
|
ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
|
|
ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
|
|
ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
|
|
|
|
if (periodic)
|
|
sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1);
|
|
else
|
|
sh_cmt_set_next(p, p->max_match_value);
|
|
}
|
|
|
|
static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
|
|
struct clock_event_device *ced)
|
|
{
|
|
struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
|
|
|
|
/* deal with old setting first */
|
|
switch (ced->mode) {
|
|
case CLOCK_EVT_MODE_PERIODIC:
|
|
case CLOCK_EVT_MODE_ONESHOT:
|
|
sh_cmt_stop(p, FLAG_CLOCKEVENT);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
switch (mode) {
|
|
case CLOCK_EVT_MODE_PERIODIC:
|
|
dev_info(&p->pdev->dev, "used for periodic clock events\n");
|
|
sh_cmt_clock_event_start(p, 1);
|
|
break;
|
|
case CLOCK_EVT_MODE_ONESHOT:
|
|
dev_info(&p->pdev->dev, "used for oneshot clock events\n");
|
|
sh_cmt_clock_event_start(p, 0);
|
|
break;
|
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
|
case CLOCK_EVT_MODE_UNUSED:
|
|
sh_cmt_stop(p, FLAG_CLOCKEVENT);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int sh_cmt_clock_event_next(unsigned long delta,
|
|
struct clock_event_device *ced)
|
|
{
|
|
struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
|
|
|
|
BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
|
|
if (likely(p->flags & FLAG_IRQCONTEXT))
|
|
p->next_match_value = delta - 1;
|
|
else
|
|
sh_cmt_set_next(p, delta - 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
|
|
{
|
|
pm_genpd_syscore_poweroff(&ced_to_sh_cmt(ced)->pdev->dev);
|
|
}
|
|
|
|
static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
|
|
{
|
|
pm_genpd_syscore_poweron(&ced_to_sh_cmt(ced)->pdev->dev);
|
|
}
|
|
|
|
static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
|
|
char *name, unsigned long rating)
|
|
{
|
|
struct clock_event_device *ced = &p->ced;
|
|
|
|
memset(ced, 0, sizeof(*ced));
|
|
|
|
ced->name = name;
|
|
ced->features = CLOCK_EVT_FEAT_PERIODIC;
|
|
ced->features |= CLOCK_EVT_FEAT_ONESHOT;
|
|
ced->rating = rating;
|
|
ced->cpumask = cpumask_of(0);
|
|
ced->set_next_event = sh_cmt_clock_event_next;
|
|
ced->set_mode = sh_cmt_clock_event_mode;
|
|
ced->suspend = sh_cmt_clock_event_suspend;
|
|
ced->resume = sh_cmt_clock_event_resume;
|
|
|
|
dev_info(&p->pdev->dev, "used for clock events\n");
|
|
clockevents_register_device(ced);
|
|
}
|
|
|
|
static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
|
|
unsigned long clockevent_rating,
|
|
unsigned long clocksource_rating)
|
|
{
|
|
if (clockevent_rating)
|
|
sh_cmt_register_clockevent(p, name, clockevent_rating);
|
|
|
|
if (clocksource_rating)
|
|
sh_cmt_register_clocksource(p, name, clocksource_rating);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
|
|
{
|
|
struct sh_timer_config *cfg = pdev->dev.platform_data;
|
|
struct resource *res;
|
|
int irq, ret;
|
|
ret = -ENXIO;
|
|
|
|
memset(p, 0, sizeof(*p));
|
|
p->pdev = pdev;
|
|
|
|
if (!cfg) {
|
|
dev_err(&p->pdev->dev, "missing platform data\n");
|
|
goto err0;
|
|
}
|
|
|
|
res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&p->pdev->dev, "failed to get I/O memory\n");
|
|
goto err0;
|
|
}
|
|
|
|
irq = platform_get_irq(p->pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&p->pdev->dev, "failed to get irq\n");
|
|
goto err0;
|
|
}
|
|
|
|
/* map memory, let mapbase point to our channel */
|
|
p->mapbase = ioremap_nocache(res->start, resource_size(res));
|
|
if (p->mapbase == NULL) {
|
|
dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
|
|
goto err0;
|
|
}
|
|
|
|
/* request irq using setup_irq() (too early for request_irq()) */
|
|
p->irqaction.name = dev_name(&p->pdev->dev);
|
|
p->irqaction.handler = sh_cmt_interrupt;
|
|
p->irqaction.dev_id = p;
|
|
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
|
|
IRQF_IRQPOLL | IRQF_NOBALANCING;
|
|
|
|
/* get hold of clock */
|
|
p->clk = clk_get(&p->pdev->dev, "cmt_fck");
|
|
if (IS_ERR(p->clk)) {
|
|
dev_err(&p->pdev->dev, "cannot get clock\n");
|
|
ret = PTR_ERR(p->clk);
|
|
goto err1;
|
|
}
|
|
|
|
p->read_control = sh_cmt_read16;
|
|
p->write_control = sh_cmt_write16;
|
|
|
|
if (resource_size(res) == 6) {
|
|
p->width = 16;
|
|
p->read_count = sh_cmt_read16;
|
|
p->write_count = sh_cmt_write16;
|
|
p->overflow_bit = 0x80;
|
|
p->clear_bits = ~0x80;
|
|
} else {
|
|
p->width = 32;
|
|
p->read_count = sh_cmt_read32;
|
|
p->write_count = sh_cmt_write32;
|
|
p->overflow_bit = 0x8000;
|
|
p->clear_bits = ~0xc000;
|
|
}
|
|
|
|
if (p->width == (sizeof(p->max_match_value) * 8))
|
|
p->max_match_value = ~0;
|
|
else
|
|
p->max_match_value = (1 << p->width) - 1;
|
|
|
|
p->match_value = p->max_match_value;
|
|
raw_spin_lock_init(&p->lock);
|
|
|
|
ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
|
|
cfg->clockevent_rating,
|
|
cfg->clocksource_rating);
|
|
if (ret) {
|
|
dev_err(&p->pdev->dev, "registration failed\n");
|
|
goto err2;
|
|
}
|
|
p->cs_enabled = false;
|
|
|
|
ret = setup_irq(irq, &p->irqaction);
|
|
if (ret) {
|
|
dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
|
|
goto err2;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, p);
|
|
|
|
return 0;
|
|
err2:
|
|
clk_put(p->clk);
|
|
|
|
err1:
|
|
iounmap(p->mapbase);
|
|
err0:
|
|
return ret;
|
|
}
|
|
|
|
static int sh_cmt_probe(struct platform_device *pdev)
|
|
{
|
|
struct sh_cmt_priv *p = platform_get_drvdata(pdev);
|
|
struct sh_timer_config *cfg = pdev->dev.platform_data;
|
|
int ret;
|
|
|
|
if (!is_early_platform_device(pdev)) {
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
}
|
|
|
|
if (p) {
|
|
dev_info(&pdev->dev, "kept as earlytimer\n");
|
|
goto out;
|
|
}
|
|
|
|
p = kmalloc(sizeof(*p), GFP_KERNEL);
|
|
if (p == NULL) {
|
|
dev_err(&pdev->dev, "failed to allocate driver data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = sh_cmt_setup(p, pdev);
|
|
if (ret) {
|
|
kfree(p);
|
|
pm_runtime_idle(&pdev->dev);
|
|
return ret;
|
|
}
|
|
if (is_early_platform_device(pdev))
|
|
return 0;
|
|
|
|
out:
|
|
if (cfg->clockevent_rating || cfg->clocksource_rating)
|
|
pm_runtime_irq_safe(&pdev->dev);
|
|
else
|
|
pm_runtime_idle(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_cmt_remove(struct platform_device *pdev)
|
|
{
|
|
return -EBUSY; /* cannot unregister clockevent and clocksource */
|
|
}
|
|
|
|
static struct platform_driver sh_cmt_device_driver = {
|
|
.probe = sh_cmt_probe,
|
|
.remove = sh_cmt_remove,
|
|
.driver = {
|
|
.name = "sh_cmt",
|
|
}
|
|
};
|
|
|
|
static int __init sh_cmt_init(void)
|
|
{
|
|
return platform_driver_register(&sh_cmt_device_driver);
|
|
}
|
|
|
|
static void __exit sh_cmt_exit(void)
|
|
{
|
|
platform_driver_unregister(&sh_cmt_device_driver);
|
|
}
|
|
|
|
early_platform_init("earlytimer", &sh_cmt_device_driver);
|
|
subsys_initcall(sh_cmt_init);
|
|
module_exit(sh_cmt_exit);
|
|
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
MODULE_DESCRIPTION("SuperH CMT Timer Driver");
|
|
MODULE_LICENSE("GPL v2");
|