![Sherman Yin](/assets/img/avatar_default.png)
When setting pin configuration in the pinctrl framework, pin_config_set() or pin_config_group_set() is called in a loop to set one configuration at a time for the specified pin or group. This patch 1) removes the loop and 2) changes the API to pass the whole pin config array to the driver. It is now up to the driver to loop through the configs. This allows the driver to potentially combine configs and reduce the number of writes to pin config registers. All c files changed have been build-tested to verify the change compiles and that the corresponding .o is successfully generated. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Matt Porter <matt.porter@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
665 lines
16 KiB
C
665 lines
16 KiB
C
/*
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* SuperH Pin Function Controller pinmux support.
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*
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* Copyright (C) 2012 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define DRV_NAME "sh-pfc"
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "core.h"
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#include "../core.h"
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#include "../pinconf.h"
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struct sh_pfc_pin_config {
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u32 type;
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};
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struct sh_pfc_pinctrl {
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struct pinctrl_dev *pctl;
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struct pinctrl_desc pctl_desc;
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struct sh_pfc *pfc;
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struct pinctrl_pin_desc *pins;
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struct sh_pfc_pin_config *configs;
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};
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static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->pfc->info->nr_groups;
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}
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static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->pfc->info->groups[selector].name;
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}
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static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
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const unsigned **pins, unsigned *num_pins)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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*pins = pmx->pfc->info->groups[selector].pins;
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*num_pins = pmx->pfc->info->groups[selector].nr_pins;
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return 0;
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}
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static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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unsigned offset)
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{
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seq_printf(s, "%s", DRV_NAME);
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}
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#ifdef CONFIG_OF
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static int sh_pfc_map_add_config(struct pinctrl_map *map,
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const char *group_or_pin,
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enum pinctrl_map_type type,
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unsigned long *configs,
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unsigned int num_configs)
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{
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unsigned long *cfgs;
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cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
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GFP_KERNEL);
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if (cfgs == NULL)
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return -ENOMEM;
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map->type = type;
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map->data.configs.group_or_pin = group_or_pin;
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map->data.configs.configs = cfgs;
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map->data.configs.num_configs = num_configs;
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return 0;
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}
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static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
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struct pinctrl_map **map,
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unsigned int *num_maps, unsigned int *index)
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{
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struct pinctrl_map *maps = *map;
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unsigned int nmaps = *num_maps;
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unsigned int idx = *index;
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unsigned int num_configs;
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const char *function = NULL;
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unsigned long *configs;
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struct property *prop;
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unsigned int num_groups;
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unsigned int num_pins;
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const char *group;
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const char *pin;
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int ret;
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/* Parse the function and configuration properties. At least a function
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* or one configuration must be specified.
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*/
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ret = of_property_read_string(np, "renesas,function", &function);
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if (ret < 0 && ret != -EINVAL) {
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dev_err(dev, "Invalid function in DT\n");
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return ret;
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}
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ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
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if (ret < 0)
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return ret;
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if (!function && num_configs == 0) {
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dev_err(dev,
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"DT node must contain at least a function or config\n");
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goto done;
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}
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/* Count the number of pins and groups and reallocate mappings. */
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ret = of_property_count_strings(np, "renesas,pins");
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if (ret == -EINVAL) {
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num_pins = 0;
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} else if (ret < 0) {
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dev_err(dev, "Invalid pins list in DT\n");
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goto done;
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} else {
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num_pins = ret;
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}
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ret = of_property_count_strings(np, "renesas,groups");
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if (ret == -EINVAL) {
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num_groups = 0;
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} else if (ret < 0) {
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dev_err(dev, "Invalid pin groups list in DT\n");
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goto done;
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} else {
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num_groups = ret;
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}
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if (!num_pins && !num_groups) {
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dev_err(dev, "No pin or group provided in DT node\n");
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ret = -ENODEV;
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goto done;
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}
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if (function)
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nmaps += num_groups;
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if (configs)
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nmaps += num_pins + num_groups;
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maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
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if (maps == NULL) {
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ret = -ENOMEM;
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goto done;
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}
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*map = maps;
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*num_maps = nmaps;
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/* Iterate over pins and groups and create the mappings. */
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of_property_for_each_string(np, "renesas,groups", prop, group) {
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if (function) {
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maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
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maps[idx].data.mux.group = group;
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maps[idx].data.mux.function = function;
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idx++;
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}
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if (configs) {
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ret = sh_pfc_map_add_config(&maps[idx], group,
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PIN_MAP_TYPE_CONFIGS_GROUP,
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configs, num_configs);
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if (ret < 0)
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goto done;
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idx++;
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}
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}
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if (!configs) {
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ret = 0;
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goto done;
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}
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of_property_for_each_string(np, "renesas,pins", prop, pin) {
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ret = sh_pfc_map_add_config(&maps[idx], pin,
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PIN_MAP_TYPE_CONFIGS_PIN,
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configs, num_configs);
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if (ret < 0)
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goto done;
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idx++;
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}
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done:
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*index = idx;
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kfree(configs);
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return ret;
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}
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static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map, unsigned num_maps)
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{
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unsigned int i;
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if (map == NULL)
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return;
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for (i = 0; i < num_maps; ++i) {
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if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
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map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
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kfree(map[i].data.configs.configs);
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}
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kfree(map);
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}
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static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np,
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struct pinctrl_map **map, unsigned *num_maps)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct device *dev = pmx->pfc->dev;
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struct device_node *child;
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unsigned int index;
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int ret;
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*map = NULL;
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*num_maps = 0;
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index = 0;
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for_each_child_of_node(np, child) {
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ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps,
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&index);
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if (ret < 0)
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goto done;
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}
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/* If no mapping has been found in child nodes try the config node. */
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if (*num_maps == 0) {
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ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index);
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if (ret < 0)
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goto done;
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}
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if (*num_maps)
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return 0;
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dev_err(dev, "no mapping found in node %s\n", np->full_name);
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ret = -EINVAL;
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done:
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if (ret < 0)
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sh_pfc_dt_free_map(pctldev, *map, *num_maps);
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return ret;
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}
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#endif /* CONFIG_OF */
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static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
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.get_groups_count = sh_pfc_get_groups_count,
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.get_group_name = sh_pfc_get_group_name,
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.get_group_pins = sh_pfc_get_group_pins,
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.pin_dbg_show = sh_pfc_pin_dbg_show,
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#ifdef CONFIG_OF
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.dt_node_to_map = sh_pfc_dt_node_to_map,
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.dt_free_map = sh_pfc_dt_free_map,
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#endif
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};
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static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->pfc->info->nr_functions;
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}
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static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->pfc->info->functions[selector].name;
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}
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static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned selector,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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*groups = pmx->pfc->info->functions[selector].groups;
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*num_groups = pmx->pfc->info->functions[selector].nr_groups;
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return 0;
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}
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static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
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unsigned group)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
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unsigned long flags;
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unsigned int i;
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int ret = 0;
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spin_lock_irqsave(&pfc->lock, flags);
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for (i = 0; i < grp->nr_pins; ++i) {
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int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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if (cfg->type != PINMUX_TYPE_NONE) {
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ret = -EBUSY;
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goto done;
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}
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}
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for (i = 0; i < grp->nr_pins; ++i) {
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ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
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if (ret < 0)
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break;
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}
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done:
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spin_unlock_irqrestore(&pfc->lock, flags);
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return ret;
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}
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static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
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unsigned group)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
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unsigned long flags;
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unsigned int i;
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spin_lock_irqsave(&pfc->lock, flags);
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for (i = 0; i < grp->nr_pins; ++i) {
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int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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cfg->type = PINMUX_TYPE_NONE;
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}
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spin_unlock_irqrestore(&pfc->lock, flags);
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}
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static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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int idx = sh_pfc_get_pin_index(pfc, offset);
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&pfc->lock, flags);
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if (cfg->type != PINMUX_TYPE_NONE) {
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dev_err(pfc->dev,
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"Pin %u is busy, can't configure it as GPIO.\n",
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offset);
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ret = -EBUSY;
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goto done;
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}
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if (!pfc->gpio) {
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/* If GPIOs are handled externally the pin mux type need to be
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* set to GPIO here.
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*/
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const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
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if (ret < 0)
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goto done;
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}
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cfg->type = PINMUX_TYPE_GPIO;
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ret = 0;
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done:
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spin_unlock_irqrestore(&pfc->lock, flags);
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return ret;
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}
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static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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int idx = sh_pfc_get_pin_index(pfc, offset);
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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unsigned long flags;
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spin_lock_irqsave(&pfc->lock, flags);
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cfg->type = PINMUX_TYPE_NONE;
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spin_unlock_irqrestore(&pfc->lock, flags);
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}
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static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset, bool input)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
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int idx = sh_pfc_get_pin_index(pfc, offset);
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const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
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unsigned long flags;
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unsigned int dir;
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int ret;
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/* Check if the requested direction is supported by the pin. Not all SoC
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* provide pin config data, so perform the check conditionally.
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*/
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if (pin->configs) {
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dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
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if (!(pin->configs & dir))
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return -EINVAL;
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}
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spin_lock_irqsave(&pfc->lock, flags);
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ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
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if (ret < 0)
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goto done;
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cfg->type = new_type;
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done:
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spin_unlock_irqrestore(&pfc->lock, flags);
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return ret;
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}
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static const struct pinmux_ops sh_pfc_pinmux_ops = {
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.get_functions_count = sh_pfc_get_functions_count,
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.get_function_name = sh_pfc_get_function_name,
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.get_function_groups = sh_pfc_get_function_groups,
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.enable = sh_pfc_func_enable,
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.disable = sh_pfc_func_disable,
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.gpio_request_enable = sh_pfc_gpio_request_enable,
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.gpio_disable_free = sh_pfc_gpio_disable_free,
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.gpio_set_direction = sh_pfc_gpio_set_direction,
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};
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/* Check whether the requested parameter is supported for a pin. */
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static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
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enum pin_config_param param)
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{
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int idx = sh_pfc_get_pin_index(pfc, _pin);
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const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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return true;
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case PIN_CONFIG_BIAS_PULL_UP:
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return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
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default:
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return false;
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}
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}
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static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
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unsigned long *config)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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enum pin_config_param param = pinconf_to_config_param(*config);
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unsigned long flags;
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unsigned int bias;
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if (!sh_pfc_pinconf_validate(pfc, _pin, param))
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return -ENOTSUPP;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (!pfc->info->ops || !pfc->info->ops->get_bias)
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return -ENOTSUPP;
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spin_lock_irqsave(&pfc->lock, flags);
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bias = pfc->info->ops->get_bias(pfc, _pin);
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spin_unlock_irqrestore(&pfc->lock, flags);
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if (bias != param)
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return -EINVAL;
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*config = 0;
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break;
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default:
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return -ENOTSUPP;
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}
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return 0;
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}
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static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
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unsigned long *configs, unsigned num_configs)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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struct sh_pfc *pfc = pmx->pfc;
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enum pin_config_param param;
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unsigned long flags;
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unsigned int i;
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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if (!sh_pfc_pinconf_validate(pfc, _pin, param))
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return -ENOTSUPP;
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switch (param) {
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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case PIN_CONFIG_BIAS_DISABLE:
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if (!pfc->info->ops || !pfc->info->ops->set_bias)
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return -ENOTSUPP;
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spin_lock_irqsave(&pfc->lock, flags);
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pfc->info->ops->set_bias(pfc, _pin, param);
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spin_unlock_irqrestore(&pfc->lock, flags);
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break;
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default:
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return -ENOTSUPP;
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}
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} /* for each config */
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return 0;
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}
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static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
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unsigned long *configs,
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unsigned num_configs)
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{
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struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
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const unsigned int *pins;
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unsigned int num_pins;
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unsigned int i;
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pins = pmx->pfc->info->groups[group].pins;
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num_pins = pmx->pfc->info->groups[group].nr_pins;
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for (i = 0; i < num_pins; ++i)
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sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
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return 0;
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}
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static const struct pinconf_ops sh_pfc_pinconf_ops = {
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.is_generic = true,
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.pin_config_get = sh_pfc_pinconf_get,
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.pin_config_set = sh_pfc_pinconf_set,
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.pin_config_group_set = sh_pfc_pinconf_group_set,
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.pin_config_config_dbg_show = pinconf_generic_dump_config,
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};
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/* PFC ranges -> pinctrl pin descs */
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static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
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{
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unsigned int i;
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/* Allocate and initialize the pins and configs arrays. */
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pmx->pins = devm_kzalloc(pfc->dev,
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sizeof(*pmx->pins) * pfc->info->nr_pins,
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GFP_KERNEL);
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if (unlikely(!pmx->pins))
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return -ENOMEM;
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pmx->configs = devm_kzalloc(pfc->dev,
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sizeof(*pmx->configs) * pfc->info->nr_pins,
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GFP_KERNEL);
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if (unlikely(!pmx->configs))
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return -ENOMEM;
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for (i = 0; i < pfc->info->nr_pins; ++i) {
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const struct sh_pfc_pin *info = &pfc->info->pins[i];
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struct sh_pfc_pin_config *cfg = &pmx->configs[i];
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struct pinctrl_pin_desc *pin = &pmx->pins[i];
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/* If the pin number is equal to -1 all pins are considered */
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pin->number = info->pin != (u16)-1 ? info->pin : i;
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pin->name = info->name;
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cfg->type = PINMUX_TYPE_NONE;
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}
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return 0;
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}
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int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
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{
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struct sh_pfc_pinctrl *pmx;
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int ret;
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pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
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if (unlikely(!pmx))
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return -ENOMEM;
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pmx->pfc = pfc;
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pfc->pinctrl = pmx;
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ret = sh_pfc_map_pins(pfc, pmx);
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if (ret < 0)
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return ret;
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pmx->pctl_desc.name = DRV_NAME;
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pmx->pctl_desc.owner = THIS_MODULE;
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pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
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pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
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pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
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pmx->pctl_desc.pins = pmx->pins;
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pmx->pctl_desc.npins = pfc->info->nr_pins;
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pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
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if (pmx->pctl == NULL)
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return -EINVAL;
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return 0;
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}
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int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
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{
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struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
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pinctrl_unregister(pmx->pctl);
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pfc->pinctrl = NULL;
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return 0;
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}
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