![Rong Wang](/assets/img/avatar_default.png)
dn and dp of USB1 can share with UART1(UART1 can route rx,tx to dn and dp pins of USB1). here we add this pinmux capability. USB1/UART1 mode selection has dedicated control register in RSC module, here we attach the register offset of private data of related pin groups. Signed-off-by: Rong Wang <Rong.Wang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
932 lines
23 KiB
C
932 lines
23 KiB
C
/*
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* pinmux driver for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/bitops.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include <asm/mach/irq.h>
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#include "pinctrl-sirf.h"
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#define DRIVER_NAME "pinmux-sirf"
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struct sirfsoc_gpio_bank {
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struct of_mm_gpio_chip chip;
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struct irq_domain *domain;
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int id;
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int parent_irq;
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spinlock_t lock;
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bool is_marco; /* for marco, some registers are different with prima2 */
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};
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static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
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static DEFINE_SPINLOCK(sgpio_lock);
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static struct sirfsoc_pin_group *sirfsoc_pin_groups;
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static int sirfsoc_pingrp_cnt;
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static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return sirfsoc_pingrp_cnt;
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}
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static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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return sirfsoc_pin_groups[selector].name;
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}
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static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
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const unsigned **pins,
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unsigned *num_pins)
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{
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*pins = sirfsoc_pin_groups[selector].pins;
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*num_pins = sirfsoc_pin_groups[selector].num_pins;
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return 0;
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}
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static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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unsigned offset)
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{
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seq_printf(s, " " DRIVER_NAME);
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}
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static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np_config,
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struct pinctrl_map **map, unsigned *num_maps)
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{
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struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
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struct device_node *np;
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struct property *prop;
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const char *function, *group;
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int ret, index = 0, count = 0;
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/* calculate number of maps required */
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for_each_child_of_node(np_config, np) {
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ret = of_property_read_string(np, "sirf,function", &function);
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if (ret < 0)
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return ret;
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ret = of_property_count_strings(np, "sirf,pins");
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if (ret < 0)
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return ret;
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count += ret;
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}
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if (!count) {
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dev_err(spmx->dev, "No child nodes passed via DT\n");
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return -ENODEV;
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}
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*map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
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if (!*map)
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return -ENOMEM;
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for_each_child_of_node(np_config, np) {
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of_property_read_string(np, "sirf,function", &function);
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of_property_for_each_string(np, "sirf,pins", prop, group) {
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(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
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(*map)[index].data.mux.group = group;
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(*map)[index].data.mux.function = function;
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index++;
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}
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}
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*num_maps = count;
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return 0;
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}
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static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map, unsigned num_maps)
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{
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kfree(map);
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}
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static struct pinctrl_ops sirfsoc_pctrl_ops = {
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.get_groups_count = sirfsoc_get_groups_count,
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.get_group_name = sirfsoc_get_group_name,
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.get_group_pins = sirfsoc_get_group_pins,
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.pin_dbg_show = sirfsoc_pin_dbg_show,
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.dt_node_to_map = sirfsoc_dt_node_to_map,
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.dt_free_map = sirfsoc_dt_free_map,
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};
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static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
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static int sirfsoc_pmxfunc_cnt;
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static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
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bool enable)
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{
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int i;
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const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
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const struct sirfsoc_muxmask *mask = mux->muxmask;
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for (i = 0; i < mux->muxmask_counts; i++) {
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u32 muxval;
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if (!spmx->is_marco) {
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muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
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if (enable)
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muxval = muxval & ~mask[i].mask;
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else
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muxval = muxval | mask[i].mask;
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writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
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} else {
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if (enable)
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writel(mask[i].mask, spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
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else
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writel(mask[i].mask, spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(mask[i].group));
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}
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}
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if (mux->funcmask && enable) {
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u32 func_en_val;
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func_en_val =
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readl(spmx->rsc_virtbase + mux->ctrlreg);
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func_en_val =
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(func_en_val & ~mux->funcmask) | (mux->funcval);
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writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
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}
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}
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static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
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unsigned group)
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{
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struct sirfsoc_pmx *spmx;
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spmx = pinctrl_dev_get_drvdata(pmxdev);
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sirfsoc_pinmux_endisable(spmx, selector, true);
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return 0;
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}
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static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
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unsigned group)
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{
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struct sirfsoc_pmx *spmx;
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spmx = pinctrl_dev_get_drvdata(pmxdev);
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sirfsoc_pinmux_endisable(spmx, selector, false);
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}
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static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
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{
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return sirfsoc_pmxfunc_cnt;
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}
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static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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return sirfsoc_pmx_functions[selector].name;
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}
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static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
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const char * const **groups,
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unsigned * const num_groups)
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{
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*groups = sirfsoc_pmx_functions[selector].groups;
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*num_groups = sirfsoc_pmx_functions[selector].num_groups;
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return 0;
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}
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static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
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struct pinctrl_gpio_range *range, unsigned offset)
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{
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struct sirfsoc_pmx *spmx;
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int group = range->id;
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u32 muxval;
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spmx = pinctrl_dev_get_drvdata(pmxdev);
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if (!spmx->is_marco) {
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muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
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muxval = muxval | (1 << (offset - range->pin_base));
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writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
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} else {
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writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(group));
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}
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return 0;
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}
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static struct pinmux_ops sirfsoc_pinmux_ops = {
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.enable = sirfsoc_pinmux_enable,
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.disable = sirfsoc_pinmux_disable,
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.get_functions_count = sirfsoc_pinmux_get_funcs_count,
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.get_function_name = sirfsoc_pinmux_get_func_name,
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.get_function_groups = sirfsoc_pinmux_get_groups,
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.gpio_request_enable = sirfsoc_pinmux_request_gpio,
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};
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static struct pinctrl_desc sirfsoc_pinmux_desc = {
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.name = DRIVER_NAME,
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.pctlops = &sirfsoc_pctrl_ops,
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.pmxops = &sirfsoc_pinmux_ops,
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.owner = THIS_MODULE,
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};
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/*
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* Todo: bind irq_chip to every pinctrl_gpio_range
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*/
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static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
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{
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.name = "sirfsoc-gpio*",
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.id = 0,
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.base = 0,
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.pin_base = 0,
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.npins = 32,
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}, {
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.name = "sirfsoc-gpio*",
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.id = 1,
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.base = 32,
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.pin_base = 32,
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.npins = 32,
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}, {
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.name = "sirfsoc-gpio*",
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.id = 2,
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.base = 64,
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.pin_base = 64,
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.npins = 32,
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}, {
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.name = "sirfsoc-gpio*",
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.id = 3,
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.base = 96,
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.pin_base = 96,
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.npins = 19,
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},
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};
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static void __iomem *sirfsoc_rsc_of_iomap(void)
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{
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const struct of_device_id rsc_ids[] = {
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{ .compatible = "sirf,prima2-rsc" },
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{ .compatible = "sirf,marco-rsc" },
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{}
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};
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struct device_node *np;
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np = of_find_matching_node(NULL, rsc_ids);
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if (!np)
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panic("unable to find compatible rsc node in dtb\n");
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return of_iomap(np, 0);
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}
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static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
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const struct of_phandle_args *gpiospec,
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u32 *flags)
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{
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if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
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return -EINVAL;
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if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
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return -EINVAL;
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if (flags)
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*flags = gpiospec->args[1];
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return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
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}
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static const struct of_device_id pinmux_ids[] = {
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{ .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
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{ .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
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{ .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
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{}
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};
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static int sirfsoc_pinmux_probe(struct platform_device *pdev)
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{
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int ret;
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struct sirfsoc_pmx *spmx;
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struct device_node *np = pdev->dev.of_node;
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const struct sirfsoc_pinctrl_data *pdata;
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int i;
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/* Create state holders etc for this driver */
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spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
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if (!spmx)
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return -ENOMEM;
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spmx->dev = &pdev->dev;
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platform_set_drvdata(pdev, spmx);
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spmx->gpio_virtbase = of_iomap(np, 0);
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if (!spmx->gpio_virtbase) {
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dev_err(&pdev->dev, "can't map gpio registers\n");
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return -ENOMEM;
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}
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spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
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if (!spmx->rsc_virtbase) {
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ret = -ENOMEM;
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dev_err(&pdev->dev, "can't map rsc registers\n");
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goto out_no_rsc_remap;
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}
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if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
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spmx->is_marco = 1;
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pdata = of_match_node(pinmux_ids, np)->data;
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sirfsoc_pin_groups = pdata->grps;
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sirfsoc_pingrp_cnt = pdata->grps_cnt;
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sirfsoc_pmx_functions = pdata->funcs;
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sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
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sirfsoc_pinmux_desc.pins = pdata->pads;
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sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
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/* Now register the pin controller and all pins it handles */
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spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
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if (!spmx->pmx) {
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dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
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ret = -EINVAL;
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goto out_no_pmx;
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}
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for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
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sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
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pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
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}
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dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
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return 0;
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out_no_pmx:
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iounmap(spmx->rsc_virtbase);
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out_no_rsc_remap:
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iounmap(spmx->gpio_virtbase);
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
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{
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int i, j;
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struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
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for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
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for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
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spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
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SIRFSOC_GPIO_CTRL(i, j));
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}
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spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
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SIRFSOC_GPIO_INT_STATUS(i));
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spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(i));
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}
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spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
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for (i = 0; i < 3; i++)
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spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
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return 0;
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}
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static int sirfsoc_pinmux_resume_noirq(struct device *dev)
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{
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int i, j;
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struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
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for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
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for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
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writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
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SIRFSOC_GPIO_CTRL(i, j));
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}
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writel(spmx->ints_regs[i], spmx->gpio_virtbase +
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SIRFSOC_GPIO_INT_STATUS(i));
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writel(spmx->paden_regs[i], spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(i));
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}
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writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
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for (i = 0; i < 3; i++)
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writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
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return 0;
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}
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static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
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.suspend_noirq = sirfsoc_pinmux_suspend_noirq,
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.resume_noirq = sirfsoc_pinmux_resume_noirq,
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.freeze_noirq = sirfsoc_pinmux_suspend_noirq,
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.restore_noirq = sirfsoc_pinmux_resume_noirq,
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};
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#endif
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static struct platform_driver sirfsoc_pinmux_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.owner = THIS_MODULE,
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.of_match_table = pinmux_ids,
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#ifdef CONFIG_PM_SLEEP
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.pm = &sirfsoc_pinmux_pm_ops,
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#endif
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},
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.probe = sirfsoc_pinmux_probe,
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};
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static int __init sirfsoc_pinmux_init(void)
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{
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return platform_driver_register(&sirfsoc_pinmux_driver);
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}
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arch_initcall(sirfsoc_pinmux_init);
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static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
|
|
struct sirfsoc_gpio_bank, chip);
|
|
|
|
return irq_create_mapping(bank->domain, offset);
|
|
}
|
|
|
|
static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
|
|
{
|
|
return gpio % SIRFSOC_GPIO_BANK_SIZE;
|
|
}
|
|
|
|
static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
|
|
{
|
|
return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
|
|
}
|
|
|
|
static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
|
|
{
|
|
return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
|
|
}
|
|
|
|
static void sirfsoc_gpio_irq_ack(struct irq_data *d)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
|
int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
|
|
u32 val, offset;
|
|
unsigned long flags;
|
|
|
|
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
|
|
|
|
spin_lock_irqsave(&sgpio_lock, flags);
|
|
|
|
val = readl(bank->chip.regs + offset);
|
|
|
|
writel(val, bank->chip.regs + offset);
|
|
|
|
spin_unlock_irqrestore(&sgpio_lock, flags);
|
|
}
|
|
|
|
static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
|
|
{
|
|
u32 val, offset;
|
|
unsigned long flags;
|
|
|
|
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
|
|
|
|
spin_lock_irqsave(&sgpio_lock, flags);
|
|
|
|
val = readl(bank->chip.regs + offset);
|
|
val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
|
|
val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
|
|
writel(val, bank->chip.regs + offset);
|
|
|
|
spin_unlock_irqrestore(&sgpio_lock, flags);
|
|
}
|
|
|
|
static void sirfsoc_gpio_irq_mask(struct irq_data *d)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
|
|
|
__sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
|
|
}
|
|
|
|
static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
|
int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
|
|
u32 val, offset;
|
|
unsigned long flags;
|
|
|
|
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
|
|
|
|
spin_lock_irqsave(&sgpio_lock, flags);
|
|
|
|
val = readl(bank->chip.regs + offset);
|
|
val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
|
|
val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
|
|
writel(val, bank->chip.regs + offset);
|
|
|
|
spin_unlock_irqrestore(&sgpio_lock, flags);
|
|
}
|
|
|
|
static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
|
int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
|
|
u32 val, offset;
|
|
unsigned long flags;
|
|
|
|
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
|
|
|
|
spin_lock_irqsave(&sgpio_lock, flags);
|
|
|
|
val = readl(bank->chip.regs + offset);
|
|
val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
|
|
|
|
switch (type) {
|
|
case IRQ_TYPE_NONE:
|
|
break;
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
|
|
val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
|
|
break;
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
|
|
val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
|
|
break;
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
|
|
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
|
|
break;
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
|
|
val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
|
|
break;
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
|
|
val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
|
|
break;
|
|
}
|
|
|
|
writel(val, bank->chip.regs + offset);
|
|
|
|
spin_unlock_irqrestore(&sgpio_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct irq_chip sirfsoc_irq_chip = {
|
|
.name = "sirf-gpio-irq",
|
|
.irq_ack = sirfsoc_gpio_irq_ack,
|
|
.irq_mask = sirfsoc_gpio_irq_mask,
|
|
.irq_unmask = sirfsoc_gpio_irq_unmask,
|
|
.irq_set_type = sirfsoc_gpio_irq_type,
|
|
};
|
|
|
|
static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
|
|
u32 status, ctrl;
|
|
int idx = 0;
|
|
struct irq_chip *chip = irq_get_chip(irq);
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
|
|
if (!status) {
|
|
printk(KERN_WARNING
|
|
"%s: gpio id %d status %#x no interrupt is flaged\n",
|
|
__func__, bank->id, status);
|
|
handle_bad_irq(irq, desc);
|
|
return;
|
|
}
|
|
|
|
while (status) {
|
|
ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
|
|
|
|
/*
|
|
* Here we must check whether the corresponding GPIO's interrupt
|
|
* has been enabled, otherwise just skip it
|
|
*/
|
|
if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
|
|
pr_debug("%s: gpio id %d idx %d happens\n",
|
|
__func__, bank->id, idx);
|
|
generic_handle_irq(irq_find_mapping(bank->domain, idx));
|
|
}
|
|
|
|
idx++;
|
|
status = status >> 1;
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
|
|
{
|
|
u32 val;
|
|
|
|
val = readl(bank->chip.regs + ctrl_offset);
|
|
val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
|
|
writel(val, bank->chip.regs + ctrl_offset);
|
|
}
|
|
|
|
static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
|
|
unsigned long flags;
|
|
|
|
if (pinctrl_request_gpio(chip->base + offset))
|
|
return -ENODEV;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
/*
|
|
* default status:
|
|
* set direction as input and mask irq
|
|
*/
|
|
sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
|
|
__sirfsoc_gpio_irq_mask(bank, offset);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
__sirfsoc_gpio_irq_mask(bank, offset);
|
|
sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
pinctrl_free_gpio(chip->base + offset);
|
|
}
|
|
|
|
static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
|
|
int idx = sirfsoc_gpio_to_offset(gpio);
|
|
unsigned long flags;
|
|
unsigned offset;
|
|
|
|
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
sirfsoc_gpio_set_input(bank, offset);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
|
|
int value)
|
|
{
|
|
u32 out_ctrl;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
out_ctrl = readl(bank->chip.regs + offset);
|
|
if (value)
|
|
out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
|
|
else
|
|
out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
|
|
|
|
out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
|
|
out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
|
|
writel(out_ctrl, bank->chip.regs + offset);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
}
|
|
|
|
static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
|
|
int idx = sirfsoc_gpio_to_offset(gpio);
|
|
u32 offset;
|
|
unsigned long flags;
|
|
|
|
offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
|
|
|
|
spin_lock_irqsave(&sgpio_lock, flags);
|
|
|
|
sirfsoc_gpio_set_output(bank, offset, value);
|
|
|
|
spin_unlock_irqrestore(&sgpio_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
|
|
}
|
|
|
|
static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
|
|
int value)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
|
|
u32 ctrl;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
|
|
if (value)
|
|
ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
|
|
else
|
|
ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
|
|
writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
}
|
|
|
|
static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
|
|
irq_hw_number_t hwirq)
|
|
{
|
|
struct sirfsoc_gpio_bank *bank = d->host_data;
|
|
|
|
if (!bank)
|
|
return -EINVAL;
|
|
|
|
irq_set_chip(irq, &sirfsoc_irq_chip);
|
|
irq_set_handler(irq, handle_level_irq);
|
|
irq_set_chip_data(irq, bank);
|
|
set_irq_flags(irq, IRQF_VALID);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
|
|
.map = sirfsoc_gpio_irq_map,
|
|
.xlate = irq_domain_xlate_twocell,
|
|
};
|
|
|
|
static void sirfsoc_gpio_set_pullup(const u32 *pullups)
|
|
{
|
|
int i, n;
|
|
const unsigned long *p = (const unsigned long *)pullups;
|
|
|
|
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
|
|
for_each_set_bit(n, p + i, BITS_PER_LONG) {
|
|
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
|
|
u32 val = readl(sgpio_bank[i].chip.regs + offset);
|
|
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
|
|
val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
|
|
writel(val, sgpio_bank[i].chip.regs + offset);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
|
|
{
|
|
int i, n;
|
|
const unsigned long *p = (const unsigned long *)pulldowns;
|
|
|
|
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
|
|
for_each_set_bit(n, p + i, BITS_PER_LONG) {
|
|
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
|
|
u32 val = readl(sgpio_bank[i].chip.regs + offset);
|
|
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
|
|
val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
|
|
writel(val, sgpio_bank[i].chip.regs + offset);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int sirfsoc_gpio_probe(struct device_node *np)
|
|
{
|
|
int i, err = 0;
|
|
struct sirfsoc_gpio_bank *bank;
|
|
void __iomem *regs;
|
|
struct platform_device *pdev;
|
|
bool is_marco = false;
|
|
|
|
u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
|
|
|
|
pdev = of_find_device_by_node(np);
|
|
if (!pdev)
|
|
return -ENODEV;
|
|
|
|
regs = of_iomap(np, 0);
|
|
if (!regs)
|
|
return -ENOMEM;
|
|
|
|
if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
|
|
is_marco = 1;
|
|
|
|
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
|
|
bank = &sgpio_bank[i];
|
|
spin_lock_init(&bank->lock);
|
|
bank->chip.gc.request = sirfsoc_gpio_request;
|
|
bank->chip.gc.free = sirfsoc_gpio_free;
|
|
bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
|
|
bank->chip.gc.get = sirfsoc_gpio_get_value;
|
|
bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
|
|
bank->chip.gc.set = sirfsoc_gpio_set_value;
|
|
bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
|
|
bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
|
|
bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
|
|
bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
|
|
bank->chip.gc.of_node = np;
|
|
bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
|
|
bank->chip.gc.of_gpio_n_cells = 2;
|
|
bank->chip.regs = regs;
|
|
bank->id = i;
|
|
bank->is_marco = is_marco;
|
|
bank->parent_irq = platform_get_irq(pdev, i);
|
|
if (bank->parent_irq < 0) {
|
|
err = bank->parent_irq;
|
|
goto out;
|
|
}
|
|
|
|
err = gpiochip_add(&bank->chip.gc);
|
|
if (err) {
|
|
pr_err("%s: error in probe function with status %d\n",
|
|
np->full_name, err);
|
|
goto out;
|
|
}
|
|
|
|
bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
|
|
&sirfsoc_gpio_irq_simple_ops, bank);
|
|
|
|
if (!bank->domain) {
|
|
pr_err("%s: Failed to create irqdomain\n", np->full_name);
|
|
err = -ENOSYS;
|
|
goto out;
|
|
}
|
|
|
|
irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
|
|
irq_set_handler_data(bank->parent_irq, bank);
|
|
}
|
|
|
|
if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
|
|
SIRFSOC_GPIO_NO_OF_BANKS))
|
|
sirfsoc_gpio_set_pullup(pullups);
|
|
|
|
if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
|
|
SIRFSOC_GPIO_NO_OF_BANKS))
|
|
sirfsoc_gpio_set_pulldown(pulldowns);
|
|
|
|
return 0;
|
|
|
|
out:
|
|
iounmap(regs);
|
|
return err;
|
|
}
|
|
|
|
static int __init sirfsoc_gpio_init(void)
|
|
{
|
|
|
|
struct device_node *np;
|
|
|
|
np = of_find_matching_node(NULL, pinmux_ids);
|
|
|
|
if (!np)
|
|
return -ENODEV;
|
|
|
|
return sirfsoc_gpio_probe(np);
|
|
}
|
|
subsys_initcall(sirfsoc_gpio_init);
|
|
|
|
MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
|
|
"Yuping Luo <yuping.luo@csr.com>, "
|
|
"Barry Song <baohua.song@csr.com>");
|
|
MODULE_DESCRIPTION("SIRFSOC pin control driver");
|
|
MODULE_LICENSE("GPL");
|