![Greg Kroah-Hartman](/assets/img/avatar_default.png)
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
389 lines
11 KiB
C
389 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_MSR_H
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#define _ASM_X86_MSR_H
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#include "msr-index.h"
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#ifndef __ASSEMBLY__
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#include <asm/asm.h>
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#include <asm/errno.h>
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#include <asm/cpumask.h>
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#include <uapi/asm/msr.h>
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struct msr {
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union {
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struct {
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u32 l;
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u32 h;
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};
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u64 q;
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};
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};
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struct msr_info {
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u32 msr_no;
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struct msr reg;
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struct msr *msrs;
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int err;
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};
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struct msr_regs_info {
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u32 *regs;
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int err;
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};
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struct saved_msr {
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bool valid;
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struct msr_info info;
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};
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struct saved_msrs {
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unsigned int num;
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struct saved_msr *array;
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};
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/*
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* both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
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* constraint has different meanings. For i386, "A" means exactly
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* edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
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* it means rax *or* rdx.
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*/
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#ifdef CONFIG_X86_64
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/* Using 64-bit values saves one instruction clearing the high half of low */
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#define DECLARE_ARGS(val, low, high) unsigned long low, high
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#define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32)
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#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
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#else
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#define DECLARE_ARGS(val, low, high) unsigned long long val
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#define EAX_EDX_VAL(val, low, high) (val)
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#define EAX_EDX_RET(val, low, high) "=A" (val)
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#endif
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#ifdef CONFIG_TRACEPOINTS
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/*
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* Be very careful with includes. This header is prone to include loops.
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*/
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#include <asm/atomic.h>
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#include <linux/tracepoint-defs.h>
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extern struct tracepoint __tracepoint_read_msr;
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extern struct tracepoint __tracepoint_write_msr;
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extern struct tracepoint __tracepoint_rdpmc;
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#define msr_tracepoint_active(t) static_key_false(&(t).key)
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extern void do_trace_write_msr(unsigned int msr, u64 val, int failed);
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extern void do_trace_read_msr(unsigned int msr, u64 val, int failed);
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extern void do_trace_rdpmc(unsigned int msr, u64 val, int failed);
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#else
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#define msr_tracepoint_active(t) false
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static inline void do_trace_write_msr(unsigned int msr, u64 val, int failed) {}
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static inline void do_trace_read_msr(unsigned int msr, u64 val, int failed) {}
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static inline void do_trace_rdpmc(unsigned int msr, u64 val, int failed) {}
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#endif
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/*
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* __rdmsr() and __wrmsr() are the two primitives which are the bare minimum MSR
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* accessors and should not have any tracing or other functionality piggybacking
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* on them - those are *purely* for accessing MSRs and nothing more. So don't even
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* think of extending them - you will be slapped with a stinking trout or a frozen
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* shark will reach you, wherever you are! You've been warned.
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*/
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static inline unsigned long long notrace __rdmsr(unsigned int msr)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("1: rdmsr\n"
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"2:\n"
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_ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_unsafe)
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: EAX_EDX_RET(val, low, high) : "c" (msr));
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return EAX_EDX_VAL(val, low, high);
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}
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static inline void notrace __wrmsr(unsigned int msr, u32 low, u32 high)
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{
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asm volatile("1: wrmsr\n"
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"2:\n"
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_ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe)
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: : "c" (msr), "a"(low), "d" (high) : "memory");
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}
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static inline unsigned long long native_read_msr(unsigned int msr)
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{
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unsigned long long val;
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val = __rdmsr(msr);
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if (msr_tracepoint_active(__tracepoint_read_msr))
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do_trace_read_msr(msr, val, 0);
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return val;
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}
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static inline unsigned long long native_read_msr_safe(unsigned int msr,
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int *err)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("2: rdmsr ; xor %[err],%[err]\n"
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"1:\n\t"
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".section .fixup,\"ax\"\n\t"
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"3: mov %[fault],%[err]\n\t"
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"xorl %%eax, %%eax\n\t"
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"xorl %%edx, %%edx\n\t"
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"jmp 1b\n\t"
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".previous\n\t"
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_ASM_EXTABLE(2b, 3b)
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: [err] "=r" (*err), EAX_EDX_RET(val, low, high)
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: "c" (msr), [fault] "i" (-EIO));
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if (msr_tracepoint_active(__tracepoint_read_msr))
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do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err);
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return EAX_EDX_VAL(val, low, high);
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}
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/* Can be uninlined because referenced by paravirt */
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static inline void notrace
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native_write_msr(unsigned int msr, u32 low, u32 high)
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{
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__wrmsr(msr, low, high);
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if (msr_tracepoint_active(__tracepoint_write_msr))
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do_trace_write_msr(msr, ((u64)high << 32 | low), 0);
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}
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/* Can be uninlined because referenced by paravirt */
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static inline int notrace
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native_write_msr_safe(unsigned int msr, u32 low, u32 high)
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{
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int err;
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asm volatile("2: wrmsr ; xor %[err],%[err]\n"
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"1:\n\t"
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".section .fixup,\"ax\"\n\t"
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"3: mov %[fault],%[err] ; jmp 1b\n\t"
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".previous\n\t"
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_ASM_EXTABLE(2b, 3b)
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: [err] "=a" (err)
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: "c" (msr), "0" (low), "d" (high),
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[fault] "i" (-EIO)
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: "memory");
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if (msr_tracepoint_active(__tracepoint_write_msr))
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do_trace_write_msr(msr, ((u64)high << 32 | low), err);
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return err;
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}
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extern int rdmsr_safe_regs(u32 regs[8]);
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extern int wrmsr_safe_regs(u32 regs[8]);
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/**
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* rdtsc() - returns the current TSC without ordering constraints
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*
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* rdtsc() returns the result of RDTSC as a 64-bit integer. The
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* only ordering constraint it supplies is the ordering implied by
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* "asm volatile": it will put the RDTSC in the place you expect. The
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* CPU can and will speculatively execute that RDTSC, though, so the
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* results can be non-monotonic if compared on different CPUs.
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*/
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static __always_inline unsigned long long rdtsc(void)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
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return EAX_EDX_VAL(val, low, high);
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}
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/**
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* rdtsc_ordered() - read the current TSC in program order
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*
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* rdtsc_ordered() returns the result of RDTSC as a 64-bit integer.
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* It is ordered like a load to a global in-memory counter. It should
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* be impossible to observe non-monotonic rdtsc_unordered() behavior
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* across multiple CPUs as long as the TSC is synced.
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*/
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static __always_inline unsigned long long rdtsc_ordered(void)
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{
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/*
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* The RDTSC instruction is not ordered relative to memory
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* access. The Intel SDM and the AMD APM are both vague on this
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* point, but empirically an RDTSC instruction can be
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* speculatively executed before prior loads. An RDTSC
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* immediately after an appropriate barrier appears to be
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* ordered as a normal load, that is, it provides the same
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* ordering guarantees as reading from a global memory location
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* that some other imaginary CPU is updating continuously with a
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* time stamp.
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*/
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alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC,
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"lfence", X86_FEATURE_LFENCE_RDTSC);
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return rdtsc();
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}
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/* Deprecated, keep it for a cycle for easier merging: */
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#define rdtscll(now) do { (now) = rdtsc_ordered(); } while (0)
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static inline unsigned long long native_read_pmc(int counter)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
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if (msr_tracepoint_active(__tracepoint_rdpmc))
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do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0);
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return EAX_EDX_VAL(val, low, high);
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#include <linux/errno.h>
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/*
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* Access to machine-specific registers (available on 586 and better only)
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* Note: the rd* operations modify the parameters directly (without using
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* pointer indirection), this allows gcc to optimize better
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*/
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#define rdmsr(msr, low, high) \
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do { \
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u64 __val = native_read_msr((msr)); \
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(void)((low) = (u32)__val); \
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(void)((high) = (u32)(__val >> 32)); \
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} while (0)
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static inline void wrmsr(unsigned int msr, u32 low, u32 high)
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{
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native_write_msr(msr, low, high);
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}
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#define rdmsrl(msr, val) \
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((val) = native_read_msr((msr)))
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static inline void wrmsrl(unsigned int msr, u64 val)
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{
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native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32));
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}
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/* wrmsr with exception handling */
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static inline int wrmsr_safe(unsigned int msr, u32 low, u32 high)
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{
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return native_write_msr_safe(msr, low, high);
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}
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/* rdmsr with exception handling */
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#define rdmsr_safe(msr, low, high) \
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({ \
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int __err; \
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u64 __val = native_read_msr_safe((msr), &__err); \
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(*low) = (u32)__val; \
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(*high) = (u32)(__val >> 32); \
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__err; \
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})
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static inline int rdmsrl_safe(unsigned int msr, unsigned long long *p)
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{
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int err;
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*p = native_read_msr_safe(msr, &err);
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return err;
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}
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#define rdpmc(counter, low, high) \
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do { \
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u64 _l = native_read_pmc((counter)); \
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(low) = (u32)_l; \
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(high) = (u32)(_l >> 32); \
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} while (0)
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#define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
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#endif /* !CONFIG_PARAVIRT */
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/*
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* 64-bit version of wrmsr_safe():
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*/
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static inline int wrmsrl_safe(u32 msr, u64 val)
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{
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return wrmsr_safe(msr, (u32)val, (u32)(val >> 32));
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}
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#define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high))
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#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
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struct msr *msrs_alloc(void);
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void msrs_free(struct msr *msrs);
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int msr_set_bit(u32 msr, u8 bit);
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int msr_clear_bit(u32 msr, u8 bit);
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#ifdef CONFIG_SMP
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int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
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int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
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void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
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void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
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int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
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int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
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int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
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int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
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#else /* CONFIG_SMP */
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static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
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{
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rdmsr(msr_no, *l, *h);
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return 0;
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}
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static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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{
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wrmsr(msr_no, l, h);
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return 0;
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}
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static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
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{
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rdmsrl(msr_no, *q);
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return 0;
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}
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static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
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{
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wrmsrl(msr_no, q);
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return 0;
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}
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static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
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struct msr *msrs)
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{
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rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
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}
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static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
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struct msr *msrs)
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{
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wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
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}
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static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
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u32 *l, u32 *h)
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{
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return rdmsr_safe(msr_no, l, h);
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}
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static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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{
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return wrmsr_safe(msr_no, l, h);
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}
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static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
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|
{
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return rdmsrl_safe(msr_no, q);
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}
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static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
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|
{
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return wrmsrl_safe(msr_no, q);
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|
}
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static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
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|
{
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|
return rdmsr_safe_regs(regs);
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|
}
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static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
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|
{
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|
return wrmsr_safe_regs(regs);
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|
}
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#endif /* CONFIG_SMP */
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|
#endif /* __ASSEMBLY__ */
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#endif /* _ASM_X86_MSR_H */
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