32830f2076
This patch (as1583) changes ehci-hcd to use an hrtimer event for unlinking empty (unused) async QHs instead of using a kernel timer. The check for empty QHs is moved to a new routine, where it doesn't require going through an entire scan of both the async and periodic schedules. And it can unlink multiple QHs at once, unlike the current code. Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
795 lines
25 KiB
C
795 lines
25 KiB
C
/*
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* Copyright (c) 2001-2002 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __LINUX_EHCI_HCD_H
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#define __LINUX_EHCI_HCD_H
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/* definitions used for the EHCI driver */
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/*
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* __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
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* __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
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* the host controller implementation.
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*
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* To facilitate the strongest possible byte-order checking from "sparse"
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* and so on, we use __leXX unless that's not practical.
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*/
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#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
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typedef __u32 __bitwise __hc32;
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typedef __u16 __bitwise __hc16;
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#else
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#define __hc32 __le32
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#define __hc16 __le16
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#endif
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/* statistics can be kept for tuning/monitoring */
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struct ehci_stats {
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/* irq usage */
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unsigned long normal;
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unsigned long error;
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unsigned long iaa;
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unsigned long lost_iaa;
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/* termination of urbs from core */
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unsigned long complete;
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unsigned long unlink;
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};
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/* ehci_hcd->lock guards shared data against other CPUs:
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* ehci_hcd: async, unlink, periodic (and shadow), ...
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* usb_host_endpoint: hcpriv
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* ehci_qh: qh_next, qtd_list
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* ehci_qtd: qtd_list
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*
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* Also, hold this lock when talking to HC registers or
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* when updating hw_* fields in shared qh/qtd/... structures.
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*/
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#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
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/*
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* ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
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* controller may be doing DMA. Lower values mean there's no DMA.
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*/
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enum ehci_rh_state {
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EHCI_RH_HALTED,
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EHCI_RH_SUSPENDED,
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EHCI_RH_RUNNING,
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EHCI_RH_STOPPING
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};
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/*
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* Timer events, ordered by increasing delay length.
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* Always update event_delays_ns[] and event_handlers[] (defined in
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* ehci-timer.c) in parallel with this list.
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*/
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enum ehci_hrtimer_event {
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EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */
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EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
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EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
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EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
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EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
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EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
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EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
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EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
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EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
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EHCI_HRTIMER_NUM_EVENTS /* Must come last */
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};
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#define EHCI_HRTIMER_NO_EVENT 99
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struct ehci_hcd { /* one per controller */
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/* timing support */
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enum ehci_hrtimer_event next_hrtimer_event;
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unsigned enabled_hrtimer_events;
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ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
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struct hrtimer hrtimer;
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int PSS_poll_count;
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int ASS_poll_count;
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int died_poll_count;
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/* glue to PCI and HCD framework */
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struct ehci_caps __iomem *caps;
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struct ehci_regs __iomem *regs;
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struct ehci_dbg_port __iomem *debug;
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__u32 hcs_params; /* cached register copy */
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spinlock_t lock;
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enum ehci_rh_state rh_state;
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/* general schedule support */
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unsigned scanning:1;
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bool intr_unlinking:1;
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bool async_unlinking:1;
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/* async schedule support */
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struct ehci_qh *async;
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struct ehci_qh *dummy; /* For AMD quirk use */
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struct ehci_qh *async_unlink;
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struct ehci_qh *async_unlink_last;
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struct ehci_qh *async_iaa;
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struct ehci_qh *qh_scan_next;
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unsigned async_unlink_cycle;
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unsigned async_count; /* async activity count */
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/* periodic schedule support */
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#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
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unsigned periodic_size;
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__hc32 *periodic; /* hw periodic table */
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dma_addr_t periodic_dma;
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unsigned i_thresh; /* uframes HC might cache */
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union ehci_shadow *pshadow; /* mirror hw periodic table */
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struct ehci_qh *intr_unlink;
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struct ehci_qh *intr_unlink_last;
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unsigned intr_unlink_cycle;
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int next_uframe; /* scan periodic, start here */
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unsigned periodic_count; /* periodic activity count */
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unsigned uframe_periodic_max; /* max periodic time per uframe */
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/* list of itds & sitds completed while clock_frame was still active */
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struct list_head cached_itd_list;
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struct ehci_itd *last_itd_to_free;
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struct list_head cached_sitd_list;
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struct ehci_sitd *last_sitd_to_free;
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unsigned clock_frame;
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/* per root hub port */
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unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
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/* bit vectors (one bit per port) */
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unsigned long bus_suspended; /* which ports were
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already suspended at the start of a bus suspend */
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unsigned long companion_ports; /* which ports are
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dedicated to the companion controller */
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unsigned long owned_ports; /* which ports are
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owned by the companion during a bus suspend */
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unsigned long port_c_suspend; /* which ports have
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the change-suspend feature turned on */
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unsigned long suspended_ports; /* which ports are
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suspended */
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unsigned long resuming_ports; /* which ports have
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started to resume */
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/* per-HC memory pools (could be per-bus, but ...) */
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struct dma_pool *qh_pool; /* qh per active urb */
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struct dma_pool *qtd_pool; /* one or more per qh */
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struct dma_pool *itd_pool; /* itd per iso urb */
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struct dma_pool *sitd_pool; /* sitd per split iso urb */
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struct timer_list watchdog;
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unsigned long actions;
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unsigned periodic_stamp;
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unsigned random_frame;
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unsigned long next_statechange;
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ktime_t last_periodic_enable;
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u32 command;
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/* SILICON QUIRKS */
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unsigned no_selective_suspend:1;
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unsigned has_fsl_port_bug:1; /* FreeScale */
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unsigned big_endian_mmio:1;
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unsigned big_endian_desc:1;
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unsigned big_endian_capbase:1;
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unsigned has_amcc_usb23:1;
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unsigned need_io_watchdog:1;
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unsigned amd_pll_fix:1;
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unsigned fs_i_thresh:1; /* Intel iso scheduling */
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unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
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unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
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unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
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/* required for usb32 quirk */
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#define OHCI_CTRL_HCFS (3 << 6)
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#define OHCI_USB_OPER (2 << 6)
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#define OHCI_USB_SUSPEND (3 << 6)
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#define OHCI_HCCTRL_OFFSET 0x4
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#define OHCI_HCCTRL_LEN 0x4
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__hc32 *ohci_hcctrl_reg;
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unsigned has_hostpc:1;
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unsigned has_lpm:1; /* support link power management */
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unsigned has_ppcd:1; /* support per-port change bits */
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u8 sbrn; /* packed release number */
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/* irq statistics */
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#ifdef EHCI_STATS
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struct ehci_stats stats;
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# define COUNT(x) do { (x)++; } while (0)
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#else
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# define COUNT(x) do {} while (0)
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#endif
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/* debug files */
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#ifdef DEBUG
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struct dentry *debug_dir;
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#endif
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};
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/* convert between an HCD pointer and the corresponding EHCI_HCD */
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static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
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{
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return (struct ehci_hcd *) (hcd->hcd_priv);
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}
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static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
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{
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return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
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}
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enum ehci_timer_action {
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TIMER_IO_WATCHDOG,
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};
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static inline void
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timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
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{
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clear_bit (action, &ehci->actions);
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}
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/*-------------------------------------------------------------------------*/
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#include <linux/usb/ehci_def.h>
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/*-------------------------------------------------------------------------*/
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#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
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/*
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* EHCI Specification 0.95 Section 3.5
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* QTD: describe data transfer components (buffer, direction, ...)
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* See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
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*
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* These are associated only with "QH" (Queue Head) structures,
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* used with control, bulk, and interrupt transfers.
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*/
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struct ehci_qtd {
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/* first part defined by EHCI spec */
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__hc32 hw_next; /* see EHCI 3.5.1 */
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__hc32 hw_alt_next; /* see EHCI 3.5.2 */
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__hc32 hw_token; /* see EHCI 3.5.3 */
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#define QTD_TOGGLE (1 << 31) /* data toggle */
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#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
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#define QTD_IOC (1 << 15) /* interrupt on complete */
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#define QTD_CERR(tok) (((tok)>>10) & 0x3)
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#define QTD_PID(tok) (((tok)>>8) & 0x3)
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#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
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#define QTD_STS_HALT (1 << 6) /* halted on error */
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#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
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#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
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#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
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#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
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#define QTD_STS_STS (1 << 1) /* split transaction state */
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#define QTD_STS_PING (1 << 0) /* issue PING? */
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#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
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#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
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#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
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__hc32 hw_buf [5]; /* see EHCI 3.5.4 */
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__hc32 hw_buf_hi [5]; /* Appendix B */
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/* the rest is HCD-private */
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dma_addr_t qtd_dma; /* qtd address */
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struct list_head qtd_list; /* sw qtd list */
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struct urb *urb; /* qtd's urb */
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size_t length; /* length of buffer */
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} __attribute__ ((aligned (32)));
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/* mask NakCnt+T in qh->hw_alt_next */
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#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
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#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
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/*-------------------------------------------------------------------------*/
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/* type tag from {qh,itd,sitd,fstn}->hw_next */
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#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
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/*
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* Now the following defines are not converted using the
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* cpu_to_le32() macro anymore, since we have to support
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* "dynamic" switching between be and le support, so that the driver
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* can be used on one system with SoC EHCI controller using big-endian
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* descriptors as well as a normal little-endian PCI EHCI controller.
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*/
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/* values for that type tag */
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#define Q_TYPE_ITD (0 << 1)
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#define Q_TYPE_QH (1 << 1)
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#define Q_TYPE_SITD (2 << 1)
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#define Q_TYPE_FSTN (3 << 1)
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/* next async queue entry, or pointer to interrupt/periodic QH */
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#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
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/* for periodic/async schedules and qtd lists, mark end of list */
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#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
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/*
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* Entries in periodic shadow table are pointers to one of four kinds
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* of data structure. That's dictated by the hardware; a type tag is
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* encoded in the low bits of the hardware's periodic schedule. Use
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* Q_NEXT_TYPE to get the tag.
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*
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* For entries in the async schedule, the type tag always says "qh".
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*/
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union ehci_shadow {
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struct ehci_qh *qh; /* Q_TYPE_QH */
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struct ehci_itd *itd; /* Q_TYPE_ITD */
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struct ehci_sitd *sitd; /* Q_TYPE_SITD */
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struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
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__hc32 *hw_next; /* (all types) */
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void *ptr;
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};
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/*-------------------------------------------------------------------------*/
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/*
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* EHCI Specification 0.95 Section 3.6
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* QH: describes control/bulk/interrupt endpoints
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* See Fig 3-7 "Queue Head Structure Layout".
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*
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* These appear in both the async and (for interrupt) periodic schedules.
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*/
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/* first part defined by EHCI spec */
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struct ehci_qh_hw {
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__hc32 hw_next; /* see EHCI 3.6.1 */
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__hc32 hw_info1; /* see EHCI 3.6.2 */
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#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
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#define QH_HEAD (1 << 15) /* Head of async reclamation list */
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#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
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#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
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#define QH_LOW_SPEED (1 << 12)
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#define QH_FULL_SPEED (0 << 12)
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#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
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__hc32 hw_info2; /* see EHCI 3.6.2 */
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#define QH_SMASK 0x000000ff
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#define QH_CMASK 0x0000ff00
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#define QH_HUBADDR 0x007f0000
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#define QH_HUBPORT 0x3f800000
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#define QH_MULT 0xc0000000
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__hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
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/* qtd overlay (hardware parts of a struct ehci_qtd) */
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__hc32 hw_qtd_next;
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__hc32 hw_alt_next;
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__hc32 hw_token;
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__hc32 hw_buf [5];
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__hc32 hw_buf_hi [5];
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} __attribute__ ((aligned(32)));
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struct ehci_qh {
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struct ehci_qh_hw *hw; /* Must come first */
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/* the rest is HCD-private */
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dma_addr_t qh_dma; /* address of qh */
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union ehci_shadow qh_next; /* ptr to qh; or periodic */
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struct list_head qtd_list; /* sw qtd list */
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struct ehci_qtd *dummy;
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struct ehci_qh *unlink_next; /* next on unlink list */
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unsigned unlink_cycle;
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unsigned stamp;
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u8 needs_rescan; /* Dequeue during giveback */
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u8 qh_state;
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#define QH_STATE_LINKED 1 /* HC sees this */
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#define QH_STATE_UNLINK 2 /* HC may still see this */
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#define QH_STATE_IDLE 3 /* HC doesn't see this */
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#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
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#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
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u8 xacterrs; /* XactErr retry counter */
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#define QH_XACTERR_MAX 32 /* XactErr retry limit */
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/* periodic schedule info */
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u8 usecs; /* intr bandwidth */
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u8 gap_uf; /* uframes split/csplit gap */
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u8 c_usecs; /* ... split completion bw */
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u16 tt_usecs; /* tt downstream bandwidth */
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unsigned short period; /* polling interval */
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unsigned short start; /* where polling starts */
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#define NO_FRAME ((unsigned short)~0) /* pick new start */
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struct usb_device *dev; /* access to TT */
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unsigned is_out:1; /* bulk or intr OUT */
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unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
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};
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/*-------------------------------------------------------------------------*/
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/* description of one iso transaction (up to 3 KB data if highspeed) */
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struct ehci_iso_packet {
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/* These will be copied to iTD when scheduling */
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u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
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__hc32 transaction; /* itd->hw_transaction[i] |= */
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u8 cross; /* buf crosses pages */
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/* for full speed OUT splits */
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u32 buf1;
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};
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/* temporary schedule data for packets from iso urbs (both speeds)
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* each packet is one logical usb transaction to the device (not TT),
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* beginning at stream->next_uframe
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*/
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struct ehci_iso_sched {
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struct list_head td_list;
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unsigned span;
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struct ehci_iso_packet packet [0];
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};
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/*
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* ehci_iso_stream - groups all (s)itds for this endpoint.
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* acts like a qh would, if EHCI had them for ISO.
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*/
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struct ehci_iso_stream {
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/* first field matches ehci_hq, but is NULL */
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struct ehci_qh_hw *hw;
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u8 bEndpointAddress;
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u8 highspeed;
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struct list_head td_list; /* queued itds/sitds */
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struct list_head free_list; /* list of unused itds/sitds */
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struct usb_device *udev;
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struct usb_host_endpoint *ep;
|
|
|
|
/* output of (re)scheduling */
|
|
int next_uframe;
|
|
__hc32 splits;
|
|
|
|
/* the rest is derived from the endpoint descriptor,
|
|
* trusting urb->interval == f(epdesc->bInterval) and
|
|
* including the extra info for hw_bufp[0..2]
|
|
*/
|
|
u8 usecs, c_usecs;
|
|
u16 interval;
|
|
u16 tt_usecs;
|
|
u16 maxp;
|
|
u16 raw_mask;
|
|
unsigned bandwidth;
|
|
|
|
/* This is used to initialize iTD's hw_bufp fields */
|
|
__hc32 buf0;
|
|
__hc32 buf1;
|
|
__hc32 buf2;
|
|
|
|
/* this is used to initialize sITD's tt info */
|
|
__hc32 address;
|
|
};
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* EHCI Specification 0.95 Section 3.3
|
|
* Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
|
|
*
|
|
* Schedule records for high speed iso xfers
|
|
*/
|
|
struct ehci_itd {
|
|
/* first part defined by EHCI spec */
|
|
__hc32 hw_next; /* see EHCI 3.3.1 */
|
|
__hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
|
|
#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
|
|
#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
|
|
#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
|
|
#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
|
|
#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
|
|
#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
|
|
|
|
#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
|
|
|
|
__hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
|
|
__hc32 hw_bufp_hi [7]; /* Appendix B */
|
|
|
|
/* the rest is HCD-private */
|
|
dma_addr_t itd_dma; /* for this itd */
|
|
union ehci_shadow itd_next; /* ptr to periodic q entry */
|
|
|
|
struct urb *urb;
|
|
struct ehci_iso_stream *stream; /* endpoint's queue */
|
|
struct list_head itd_list; /* list of stream's itds */
|
|
|
|
/* any/all hw_transactions here may be used by that urb */
|
|
unsigned frame; /* where scheduled */
|
|
unsigned pg;
|
|
unsigned index[8]; /* in urb->iso_frame_desc */
|
|
} __attribute__ ((aligned (32)));
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* EHCI Specification 0.95 Section 3.4
|
|
* siTD, aka split-transaction isochronous Transfer Descriptor
|
|
* ... describe full speed iso xfers through TT in hubs
|
|
* see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
|
|
*/
|
|
struct ehci_sitd {
|
|
/* first part defined by EHCI spec */
|
|
__hc32 hw_next;
|
|
/* uses bit field macros above - see EHCI 0.95 Table 3-8 */
|
|
__hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
|
|
__hc32 hw_uframe; /* EHCI table 3-10 */
|
|
__hc32 hw_results; /* EHCI table 3-11 */
|
|
#define SITD_IOC (1 << 31) /* interrupt on completion */
|
|
#define SITD_PAGE (1 << 30) /* buffer 0/1 */
|
|
#define SITD_LENGTH(x) (0x3ff & ((x)>>16))
|
|
#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
|
|
#define SITD_STS_ERR (1 << 6) /* error from TT */
|
|
#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
|
|
#define SITD_STS_BABBLE (1 << 4) /* device was babbling */
|
|
#define SITD_STS_XACT (1 << 3) /* illegal IN response */
|
|
#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
|
|
#define SITD_STS_STS (1 << 1) /* split transaction state */
|
|
|
|
#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
|
|
|
|
__hc32 hw_buf [2]; /* EHCI table 3-12 */
|
|
__hc32 hw_backpointer; /* EHCI table 3-13 */
|
|
__hc32 hw_buf_hi [2]; /* Appendix B */
|
|
|
|
/* the rest is HCD-private */
|
|
dma_addr_t sitd_dma;
|
|
union ehci_shadow sitd_next; /* ptr to periodic q entry */
|
|
|
|
struct urb *urb;
|
|
struct ehci_iso_stream *stream; /* endpoint's queue */
|
|
struct list_head sitd_list; /* list of stream's sitds */
|
|
unsigned frame;
|
|
unsigned index;
|
|
} __attribute__ ((aligned (32)));
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* EHCI Specification 0.96 Section 3.7
|
|
* Periodic Frame Span Traversal Node (FSTN)
|
|
*
|
|
* Manages split interrupt transactions (using TT) that span frame boundaries
|
|
* into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
|
|
* makes the HC jump (back) to a QH to scan for fs/ls QH completions until
|
|
* it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
|
|
*/
|
|
struct ehci_fstn {
|
|
__hc32 hw_next; /* any periodic q entry */
|
|
__hc32 hw_prev; /* qh or EHCI_LIST_END */
|
|
|
|
/* the rest is HCD-private */
|
|
dma_addr_t fstn_dma;
|
|
union ehci_shadow fstn_next; /* ptr to periodic q entry */
|
|
} __attribute__ ((aligned (32)));
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/* Prepare the PORTSC wakeup flags during controller suspend/resume */
|
|
|
|
#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
|
|
ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
|
|
|
|
#define ehci_prepare_ports_for_controller_resume(ehci) \
|
|
ehci_adjust_port_wakeup_flags(ehci, false, false);
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
|
|
|
|
/*
|
|
* Some EHCI controllers have a Transaction Translator built into the
|
|
* root hub. This is a non-standard feature. Each controller will need
|
|
* to add code to the following inline functions, and call them as
|
|
* needed (mostly in root hub code).
|
|
*/
|
|
|
|
#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
|
|
|
|
/* Returns the speed of a device attached to a port on the root hub. */
|
|
static inline unsigned int
|
|
ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
|
|
{
|
|
if (ehci_is_TDI(ehci)) {
|
|
switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
|
|
case 0:
|
|
return 0;
|
|
case 1:
|
|
return USB_PORT_STAT_LOW_SPEED;
|
|
case 2:
|
|
default:
|
|
return USB_PORT_STAT_HIGH_SPEED;
|
|
}
|
|
}
|
|
return USB_PORT_STAT_HIGH_SPEED;
|
|
}
|
|
|
|
#else
|
|
|
|
#define ehci_is_TDI(e) (0)
|
|
|
|
#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
|
|
#endif
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
#ifdef CONFIG_PPC_83xx
|
|
/* Some Freescale processors have an erratum in which the TT
|
|
* port number in the queue head was 0..N-1 instead of 1..N.
|
|
*/
|
|
#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
|
|
#else
|
|
#define ehci_has_fsl_portno_bug(e) (0)
|
|
#endif
|
|
|
|
/*
|
|
* While most USB host controllers implement their registers in
|
|
* little-endian format, a minority (celleb companion chip) implement
|
|
* them in big endian format.
|
|
*
|
|
* This attempts to support either format at compile time without a
|
|
* runtime penalty, or both formats with the additional overhead
|
|
* of checking a flag bit.
|
|
*
|
|
* ehci_big_endian_capbase is a special quirk for controllers that
|
|
* implement the HC capability registers as separate registers and not
|
|
* as fields of a 32-bit register.
|
|
*/
|
|
|
|
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
|
|
#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
|
|
#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
|
|
#else
|
|
#define ehci_big_endian_mmio(e) 0
|
|
#define ehci_big_endian_capbase(e) 0
|
|
#endif
|
|
|
|
/*
|
|
* Big-endian read/write functions are arch-specific.
|
|
* Other arches can be added if/when they're needed.
|
|
*/
|
|
#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
|
|
#define readl_be(addr) __raw_readl((__force unsigned *)addr)
|
|
#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
|
|
#endif
|
|
|
|
static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
|
|
__u32 __iomem * regs)
|
|
{
|
|
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
|
|
return ehci_big_endian_mmio(ehci) ?
|
|
readl_be(regs) :
|
|
readl(regs);
|
|
#else
|
|
return readl(regs);
|
|
#endif
|
|
}
|
|
|
|
static inline void ehci_writel(const struct ehci_hcd *ehci,
|
|
const unsigned int val, __u32 __iomem *regs)
|
|
{
|
|
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
|
|
ehci_big_endian_mmio(ehci) ?
|
|
writel_be(val, regs) :
|
|
writel(val, regs);
|
|
#else
|
|
writel(val, regs);
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* On certain ppc-44x SoC there is a HW issue, that could only worked around with
|
|
* explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
|
|
* Other common bits are dependent on has_amcc_usb23 quirk flag.
|
|
*/
|
|
#ifdef CONFIG_44x
|
|
static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
|
|
{
|
|
u32 hc_control;
|
|
|
|
hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
|
|
if (operational)
|
|
hc_control |= OHCI_USB_OPER;
|
|
else
|
|
hc_control |= OHCI_USB_SUSPEND;
|
|
|
|
writel_be(hc_control, ehci->ohci_hcctrl_reg);
|
|
(void) readl_be(ehci->ohci_hcctrl_reg);
|
|
}
|
|
#else
|
|
static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
|
|
{ }
|
|
#endif
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* The AMCC 440EPx not only implements its EHCI registers in big-endian
|
|
* format, but also its DMA data structures (descriptors).
|
|
*
|
|
* EHCI controllers accessed through PCI work normally (little-endian
|
|
* everywhere), so we won't bother supporting a BE-only mode for now.
|
|
*/
|
|
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
|
|
#define ehci_big_endian_desc(e) ((e)->big_endian_desc)
|
|
|
|
/* cpu to ehci */
|
|
static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
|
|
{
|
|
return ehci_big_endian_desc(ehci)
|
|
? (__force __hc32)cpu_to_be32(x)
|
|
: (__force __hc32)cpu_to_le32(x);
|
|
}
|
|
|
|
/* ehci to cpu */
|
|
static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
|
|
{
|
|
return ehci_big_endian_desc(ehci)
|
|
? be32_to_cpu((__force __be32)x)
|
|
: le32_to_cpu((__force __le32)x);
|
|
}
|
|
|
|
static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
|
|
{
|
|
return ehci_big_endian_desc(ehci)
|
|
? be32_to_cpup((__force __be32 *)x)
|
|
: le32_to_cpup((__force __le32 *)x);
|
|
}
|
|
|
|
#else
|
|
|
|
/* cpu to ehci */
|
|
static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
|
|
{
|
|
return cpu_to_le32(x);
|
|
}
|
|
|
|
/* ehci to cpu */
|
|
static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
|
|
{
|
|
return le32_to_cpu(x);
|
|
}
|
|
|
|
static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
|
|
{
|
|
return le32_to_cpup(x);
|
|
}
|
|
|
|
#endif
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
/* For working around the MosChip frame-index-register bug */
|
|
static unsigned ehci_read_frame_index(struct ehci_hcd *ehci);
|
|
|
|
#else
|
|
|
|
static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
|
|
{
|
|
return ehci_readl(ehci, &ehci->regs->frame_index);
|
|
}
|
|
|
|
#endif
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
#ifndef DEBUG
|
|
#define STUB_DEBUG_FILES
|
|
#endif /* DEBUG */
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
#endif /* __LINUX_EHCI_HCD_H */
|