226 lines
6.1 KiB
Plaintext
226 lines
6.1 KiB
Plaintext
/*
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* Copyright (C) 2016 ARM Ltd.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <arm/sunxi-h3-h5.dtsi>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu",
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"arm,armv8-pmuv3";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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syscon: system-control@1c00000 {
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compatible = "allwinner,sun50i-h5-system-control";
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reg = <0x01c00000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_c1: sram@18000 {
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compatible = "mmio-sram";
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reg = <0x00018000 0x1c000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00018000 0x1c000>;
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ve_sram: sram-section@0 {
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compatible = "allwinner,sun50i-h5-sram-c1",
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"allwinner,sun4i-a10-sram-c1";
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reg = <0x000000 0x1c000>;
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};
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};
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};
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video-codec@1c0e000 {
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compatible = "allwinner,sun50i-h5-video-engine";
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reg = <0x01c0e000 0x1000>;
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clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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<&ccu CLK_DRAM_VE>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_BUS_VE>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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allwinner,sram = <&ve_sram 1>;
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};
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mali: gpu@1e80000 {
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compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
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reg = <0x01e80000 0x30000>;
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/*
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* While the datasheet lists an interrupt for the
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* PMU, the actual silicon does not have the PMU
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* block. Reads all return zero, and writes are
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* ignored.
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*/
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp",
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"gpmmu",
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"pp",
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"pp0",
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"ppmmu0",
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"pp1",
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"ppmmu1",
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"pp2",
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"ppmmu2",
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"pp3",
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"ppmmu3",
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"pmu";
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clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
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clock-names = "bus", "core";
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resets = <&ccu RST_BUS_GPU>;
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assigned-clocks = <&ccu CLK_GPU>;
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assigned-clock-rates = <384000000>;
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};
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};
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};
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&ccu {
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compatible = "allwinner,sun50i-h5-ccu";
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};
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&display_clocks {
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compatible = "allwinner,sun50i-h5-de2-clk";
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};
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&mmc0 {
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compatible = "allwinner,sun50i-h5-mmc",
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"allwinner,sun50i-a64-mmc";
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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};
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&mmc1 {
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compatible = "allwinner,sun50i-h5-mmc",
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"allwinner,sun50i-a64-mmc";
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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};
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&mmc2 {
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compatible = "allwinner,sun50i-h5-emmc",
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"allwinner,sun50i-a64-emmc";
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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};
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&pio {
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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compatible = "allwinner,sun50i-h5-pinctrl";
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};
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&rtc {
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compatible = "allwinner,sun50i-h5-rtc";
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};
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&sid {
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compatible = "allwinner,sun50i-h5-sid";
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};
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