c075b6f2d3
POKE32 and PEEK32 have been replaced by inlined functions poke32 and peek32. Having inline functions instead of macros help to get the correct type-checking and avoid the possible precedence issues reported by checkpatch. Signed-off-by: Matthieu Simon <gmatthsim@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
224 lines
6.6 KiB
C
224 lines
6.6 KiB
C
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#include "ddk750_reg.h"
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#include "ddk750_mode.h"
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#include "ddk750_chip.h"
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/*
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* SM750LE only:
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* This function takes care extra registers and bit fields required to set
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* up a mode in SM750LE
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*
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* Explanation about Display Control register:
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* HW only supports 7 predefined pixel clocks, and clock select is
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* in bit 29:27 of Display Control register.
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*/
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static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, unsigned long dispControl)
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{
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unsigned long x, y;
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x = pModeParam->horizontal_display_end;
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y = pModeParam->vertical_display_end;
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/*
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* SM750LE has to set up the top-left and bottom-right
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* registers as well.
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* Note that normal SM750/SM718 only use those two register for
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* auto-centering mode.
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*/
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poke32(CRT_AUTO_CENTERING_TL, 0);
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poke32(CRT_AUTO_CENTERING_BR,
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(((y - 1) << CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT) &
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CRT_AUTO_CENTERING_BR_BOTTOM_MASK) |
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((x - 1) & CRT_AUTO_CENTERING_BR_RIGHT_MASK));
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/*
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* Assume common fields in dispControl have been properly set before
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* calling this function.
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* This function only sets the extra fields in dispControl.
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*/
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/* Clear bit 29:27 of display control register */
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dispControl &= ~CRT_DISPLAY_CTRL_CLK_MASK;
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/* Set bit 29:27 of display control register for the right clock */
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/* Note that SM750LE only need to supported 7 resolutions. */
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if (x == 800 && y == 600)
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dispControl |= CRT_DISPLAY_CTRL_CLK_PLL41;
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else if (x == 1024 && y == 768)
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dispControl |= CRT_DISPLAY_CTRL_CLK_PLL65;
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else if (x == 1152 && y == 864)
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dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80;
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else if (x == 1280 && y == 768)
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dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80;
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else if (x == 1280 && y == 720)
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dispControl |= CRT_DISPLAY_CTRL_CLK_PLL74;
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else if (x == 1280 && y == 960)
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dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108;
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else if (x == 1280 && y == 1024)
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dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108;
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else /* default to VGA clock */
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dispControl |= CRT_DISPLAY_CTRL_CLK_PLL25;
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/* Set bit 25:24 of display controller */
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dispControl |= (CRT_DISPLAY_CTRL_CRTSELECT | CRT_DISPLAY_CTRL_RGBBIT);
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/* Set bit 14 of display controller */
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dispControl |= DISPLAY_CTRL_CLOCK_PHASE;
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poke32(CRT_DISPLAY_CTRL, dispControl);
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return dispControl;
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}
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/* only timing related registers will be programed */
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static int programModeRegisters(mode_parameter_t *pModeParam,
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struct pll_value *pll)
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{
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int ret = 0;
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int cnt = 0;
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unsigned int tmp, reg;
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if (pll->clockType == SECONDARY_PLL) {
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/* programe secondary pixel clock */
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poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll));
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poke32(CRT_HORIZONTAL_TOTAL,
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(((pModeParam->horizontal_total - 1) <<
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CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) &
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CRT_HORIZONTAL_TOTAL_TOTAL_MASK) |
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((pModeParam->horizontal_display_end - 1) &
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CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK));
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poke32(CRT_HORIZONTAL_SYNC,
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((pModeParam->horizontal_sync_width <<
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CRT_HORIZONTAL_SYNC_WIDTH_SHIFT) &
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CRT_HORIZONTAL_SYNC_WIDTH_MASK) |
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((pModeParam->horizontal_sync_start - 1) &
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CRT_HORIZONTAL_SYNC_START_MASK));
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poke32(CRT_VERTICAL_TOTAL,
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(((pModeParam->vertical_total - 1) <<
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CRT_VERTICAL_TOTAL_TOTAL_SHIFT) &
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CRT_VERTICAL_TOTAL_TOTAL_MASK) |
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((pModeParam->vertical_display_end - 1) &
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CRT_VERTICAL_TOTAL_DISPLAY_END_MASK));
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poke32(CRT_VERTICAL_SYNC,
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((pModeParam->vertical_sync_height <<
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CRT_VERTICAL_SYNC_HEIGHT_SHIFT) &
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CRT_VERTICAL_SYNC_HEIGHT_MASK) |
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((pModeParam->vertical_sync_start - 1) &
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CRT_VERTICAL_SYNC_START_MASK));
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tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
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if (pModeParam->vertical_sync_polarity)
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tmp |= DISPLAY_CTRL_VSYNC_PHASE;
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if (pModeParam->horizontal_sync_polarity)
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tmp |= DISPLAY_CTRL_HSYNC_PHASE;
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if (sm750_get_chip_type() == SM750LE) {
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displayControlAdjust_SM750LE(pModeParam, tmp);
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} else {
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reg = peek32(CRT_DISPLAY_CTRL) &
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~(DISPLAY_CTRL_VSYNC_PHASE |
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DISPLAY_CTRL_HSYNC_PHASE |
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DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE);
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poke32(CRT_DISPLAY_CTRL, tmp | reg);
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}
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} else if (pll->clockType == PRIMARY_PLL) {
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unsigned int reserved;
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poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll));
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reg = ((pModeParam->horizontal_total - 1) <<
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PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) &
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PANEL_HORIZONTAL_TOTAL_TOTAL_MASK;
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reg |= ((pModeParam->horizontal_display_end - 1) &
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PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK);
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poke32(PANEL_HORIZONTAL_TOTAL, reg);
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poke32(PANEL_HORIZONTAL_SYNC,
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((pModeParam->horizontal_sync_width <<
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PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT) &
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PANEL_HORIZONTAL_SYNC_WIDTH_MASK) |
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((pModeParam->horizontal_sync_start - 1) &
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PANEL_HORIZONTAL_SYNC_START_MASK));
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poke32(PANEL_VERTICAL_TOTAL,
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(((pModeParam->vertical_total - 1) <<
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PANEL_VERTICAL_TOTAL_TOTAL_SHIFT) &
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PANEL_VERTICAL_TOTAL_TOTAL_MASK) |
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((pModeParam->vertical_display_end - 1) &
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PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK));
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poke32(PANEL_VERTICAL_SYNC,
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((pModeParam->vertical_sync_height <<
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PANEL_VERTICAL_SYNC_HEIGHT_SHIFT) &
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PANEL_VERTICAL_SYNC_HEIGHT_MASK) |
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((pModeParam->vertical_sync_start - 1) &
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PANEL_VERTICAL_SYNC_START_MASK));
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tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
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if (pModeParam->vertical_sync_polarity)
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tmp |= DISPLAY_CTRL_VSYNC_PHASE;
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if (pModeParam->horizontal_sync_polarity)
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tmp |= DISPLAY_CTRL_HSYNC_PHASE;
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if (pModeParam->clock_phase_polarity)
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tmp |= DISPLAY_CTRL_CLOCK_PHASE;
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reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK |
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PANEL_DISPLAY_CTRL_VSYNC;
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reg = (peek32(PANEL_DISPLAY_CTRL) & ~reserved) &
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~(DISPLAY_CTRL_CLOCK_PHASE | DISPLAY_CTRL_VSYNC_PHASE |
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DISPLAY_CTRL_HSYNC_PHASE | DISPLAY_CTRL_TIMING |
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DISPLAY_CTRL_PLANE);
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/*
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* May a hardware bug or just my test chip (not confirmed).
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* PANEL_DISPLAY_CTRL register seems requiring few writes
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* before a value can be successfully written in.
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* Added some masks to mask out the reserved bits.
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* Note: This problem happens by design. The hardware will wait
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* for the next vertical sync to turn on/off the plane.
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*/
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poke32(PANEL_DISPLAY_CTRL, tmp | reg);
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while ((peek32(PANEL_DISPLAY_CTRL) & ~reserved) !=
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(tmp | reg)) {
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cnt++;
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if (cnt > 1000)
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break;
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poke32(PANEL_DISPLAY_CTRL, tmp | reg);
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}
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} else {
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ret = -1;
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}
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return ret;
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}
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int ddk750_setModeTiming(mode_parameter_t *parm, clock_type_t clock)
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{
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struct pll_value pll;
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unsigned int uiActualPixelClk;
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pll.inputFreq = DEFAULT_INPUT_CLOCK;
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pll.clockType = clock;
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uiActualPixelClk = sm750_calc_pll_value(parm->pixel_clock, &pll);
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if (sm750_get_chip_type() == SM750LE) {
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/* set graphic mode via IO method */
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outb_p(0x88, 0x3d4);
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outb_p(0x06, 0x3d5);
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}
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programModeRegisters(parm, &pll);
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return 0;
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}
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