![Luis R. Rodriguez](/assets/img/avatar_default.png)
Rename dma_*_writecombine() to dma_*_wc(), so that the naming is coherent across the various write-combining APIs. Keep the old names for compatibility for a while, these can be removed at a later time. A guard is left to enable backporting of the rename, and later remove of the old mapping defines seemlessly. Build tested successfully with allmodconfig. The following Coccinelle SmPL patch was used for this simple transformation: @ rename_dma_alloc_writecombine @ expression dev, size, dma_addr, gfp; @@ -dma_alloc_writecombine(dev, size, dma_addr, gfp) +dma_alloc_wc(dev, size, dma_addr, gfp) @ rename_dma_free_writecombine @ expression dev, size, cpu_addr, dma_addr; @@ -dma_free_writecombine(dev, size, cpu_addr, dma_addr) +dma_free_wc(dev, size, cpu_addr, dma_addr) @ rename_dma_mmap_writecombine @ expression dev, vma, cpu_addr, dma_addr, size; @@ -dma_mmap_writecombine(dev, vma, cpu_addr, dma_addr, size) +dma_mmap_wc(dev, vma, cpu_addr, dma_addr, size) We also keep the old names as compatibility helpers, and guard against their definition to make backporting easier. Generated-by: Coccinelle SmPL Suggested-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: airlied@linux.ie Cc: akpm@linux-foundation.org Cc: benh@kernel.crashing.org Cc: bhelgaas@google.com Cc: bp@suse.de Cc: dan.j.williams@intel.com Cc: daniel.vetter@ffwll.ch Cc: dhowells@redhat.com Cc: julia.lawall@lip6.fr Cc: konrad.wilk@oracle.com Cc: linux-fbdev@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: luto@amacapital.net Cc: mst@redhat.com Cc: tomi.valkeinen@ti.com Cc: toshi.kani@hp.com Cc: vinod.koul@intel.com Cc: xen-devel@lists.xensource.com Link: http://lkml.kernel.org/r/1453516462-4844-1-git-send-email-mcgrof@do-not-panic.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
765 lines
19 KiB
C
765 lines
19 KiB
C
/*
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*
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* Copyright (c) 2009 Nuvoton technology corporation
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Description:
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* Nuvoton LCD Controller Driver
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* Author:
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* Wang Qiang (rurality.linux@gmail.com) 2009/12/11
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/tty.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/workqueue.h>
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#include <linux/wait.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/io.h>
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#include <linux/pm.h>
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#include <linux/device.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-ldm.h>
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#include <linux/platform_data/video-nuc900fb.h>
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#include "nuc900fb.h"
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/*
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* Initialize the nuc900 video (dual) buffer address
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*/
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static void nuc900fb_set_lcdaddr(struct fb_info *info)
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{
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struct nuc900fb_info *fbi = info->par;
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void __iomem *regs = fbi->io;
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unsigned long vbaddr1, vbaddr2;
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vbaddr1 = info->fix.smem_start;
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vbaddr2 = info->fix.smem_start;
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vbaddr2 += info->fix.line_length * info->var.yres;
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/* set frambuffer start phy addr*/
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writel(vbaddr1, regs + REG_LCM_VA_BADDR0);
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writel(vbaddr2, regs + REG_LCM_VA_BADDR1);
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writel(fbi->regs.lcd_va_fbctrl, regs + REG_LCM_VA_FBCTRL);
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writel(fbi->regs.lcd_va_scale, regs + REG_LCM_VA_SCALE);
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}
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/*
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* calculate divider for lcd div
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*/
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static unsigned int nuc900fb_calc_pixclk(struct nuc900fb_info *fbi,
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unsigned long pixclk)
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{
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unsigned long clk = fbi->clk_rate;
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unsigned long long div;
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/* pixclk is in picseconds. our clock is in Hz*/
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/* div = (clk * pixclk)/10^12 */
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div = (unsigned long long)clk * pixclk;
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div >>= 12;
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do_div(div, 625 * 625UL * 625);
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dev_dbg(fbi->dev, "pixclk %ld, divisor is %lld\n", pixclk, div);
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return div;
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}
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/*
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* Check the video params of 'var'.
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*/
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static int nuc900fb_check_var(struct fb_var_screeninfo *var,
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struct fb_info *info)
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{
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struct nuc900fb_info *fbi = info->par;
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struct nuc900fb_mach_info *mach_info = dev_get_platdata(fbi->dev);
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struct nuc900fb_display *display = NULL;
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struct nuc900fb_display *default_display = mach_info->displays +
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mach_info->default_display;
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int i;
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dev_dbg(fbi->dev, "check_var(var=%p, info=%p)\n", var, info);
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/* validate x/y resolution */
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/* choose default mode if possible */
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if (var->xres == default_display->xres &&
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var->yres == default_display->yres &&
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var->bits_per_pixel == default_display->bpp)
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display = default_display;
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else
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for (i = 0; i < mach_info->num_displays; i++)
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if (var->xres == mach_info->displays[i].xres &&
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var->yres == mach_info->displays[i].yres &&
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var->bits_per_pixel == mach_info->displays[i].bpp) {
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display = mach_info->displays + i;
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break;
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}
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if (display == NULL) {
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printk(KERN_ERR "wrong resolution or depth %dx%d at %d bit per pixel\n",
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var->xres, var->yres, var->bits_per_pixel);
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return -EINVAL;
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}
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/* it should be the same size as the display */
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var->xres_virtual = display->xres;
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var->yres_virtual = display->yres;
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var->height = display->height;
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var->width = display->width;
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/* copy lcd settings */
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var->pixclock = display->pixclock;
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var->left_margin = display->left_margin;
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var->right_margin = display->right_margin;
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var->upper_margin = display->upper_margin;
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var->lower_margin = display->lower_margin;
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var->vsync_len = display->vsync_len;
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var->hsync_len = display->hsync_len;
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var->transp.offset = 0;
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var->transp.length = 0;
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fbi->regs.lcd_dccs = display->dccs;
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fbi->regs.lcd_device_ctrl = display->devctl;
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fbi->regs.lcd_va_fbctrl = display->fbctrl;
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fbi->regs.lcd_va_scale = display->scale;
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/* set R/G/B possions */
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switch (var->bits_per_pixel) {
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case 1:
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case 2:
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case 4:
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case 8:
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default:
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var->red.offset = 0;
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var->red.length = var->bits_per_pixel;
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var->green = var->red;
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var->blue = var->red;
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break;
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case 12:
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var->red.length = 4;
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var->green.length = 4;
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var->blue.length = 4;
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var->red.offset = 8;
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var->green.offset = 4;
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var->blue.offset = 0;
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break;
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case 16:
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var->red.length = 5;
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var->green.length = 6;
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var->blue.length = 5;
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var->red.offset = 11;
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var->green.offset = 5;
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var->blue.offset = 0;
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break;
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case 18:
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var->red.length = 6;
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var->green.length = 6;
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var->blue.length = 6;
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var->red.offset = 12;
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var->green.offset = 6;
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var->blue.offset = 0;
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break;
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case 32:
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var->red.length = 8;
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var->green.length = 8;
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var->blue.length = 8;
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var->red.offset = 16;
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var->green.offset = 8;
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var->blue.offset = 0;
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break;
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}
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return 0;
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}
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/*
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* Calculate lcd register values from var setting & save into hw
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*/
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static void nuc900fb_calculate_lcd_regs(const struct fb_info *info,
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struct nuc900fb_hw *regs)
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{
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const struct fb_var_screeninfo *var = &info->var;
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int vtt = var->height + var->upper_margin + var->lower_margin;
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int htt = var->width + var->left_margin + var->right_margin;
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int hsync = var->width + var->right_margin;
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int vsync = var->height + var->lower_margin;
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regs->lcd_crtc_size = LCM_CRTC_SIZE_VTTVAL(vtt) |
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LCM_CRTC_SIZE_HTTVAL(htt);
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regs->lcd_crtc_dend = LCM_CRTC_DEND_VDENDVAL(var->height) |
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LCM_CRTC_DEND_HDENDVAL(var->width);
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regs->lcd_crtc_hr = LCM_CRTC_HR_EVAL(var->width + 5) |
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LCM_CRTC_HR_SVAL(var->width + 1);
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regs->lcd_crtc_hsync = LCM_CRTC_HSYNC_EVAL(hsync + var->hsync_len) |
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LCM_CRTC_HSYNC_SVAL(hsync);
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regs->lcd_crtc_vr = LCM_CRTC_VR_EVAL(vsync + var->vsync_len) |
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LCM_CRTC_VR_SVAL(vsync);
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}
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/*
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* Activate (set) the controller from the given framebuffer
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* information
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*/
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static void nuc900fb_activate_var(struct fb_info *info)
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{
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struct nuc900fb_info *fbi = info->par;
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void __iomem *regs = fbi->io;
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struct fb_var_screeninfo *var = &info->var;
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int clkdiv;
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clkdiv = nuc900fb_calc_pixclk(fbi, var->pixclock) - 1;
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if (clkdiv < 0)
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clkdiv = 0;
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nuc900fb_calculate_lcd_regs(info, &fbi->regs);
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/* set the new lcd registers*/
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dev_dbg(fbi->dev, "new lcd register set:\n");
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dev_dbg(fbi->dev, "dccs = 0x%08x\n", fbi->regs.lcd_dccs);
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dev_dbg(fbi->dev, "dev_ctl = 0x%08x\n", fbi->regs.lcd_device_ctrl);
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dev_dbg(fbi->dev, "crtc_size = 0x%08x\n", fbi->regs.lcd_crtc_size);
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dev_dbg(fbi->dev, "crtc_dend = 0x%08x\n", fbi->regs.lcd_crtc_dend);
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dev_dbg(fbi->dev, "crtc_hr = 0x%08x\n", fbi->regs.lcd_crtc_hr);
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dev_dbg(fbi->dev, "crtc_hsync = 0x%08x\n", fbi->regs.lcd_crtc_hsync);
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dev_dbg(fbi->dev, "crtc_vr = 0x%08x\n", fbi->regs.lcd_crtc_vr);
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writel(fbi->regs.lcd_device_ctrl, regs + REG_LCM_DEV_CTRL);
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writel(fbi->regs.lcd_crtc_size, regs + REG_LCM_CRTC_SIZE);
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writel(fbi->regs.lcd_crtc_dend, regs + REG_LCM_CRTC_DEND);
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writel(fbi->regs.lcd_crtc_hr, regs + REG_LCM_CRTC_HR);
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writel(fbi->regs.lcd_crtc_hsync, regs + REG_LCM_CRTC_HSYNC);
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writel(fbi->regs.lcd_crtc_vr, regs + REG_LCM_CRTC_VR);
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/* set lcd address pointers */
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nuc900fb_set_lcdaddr(info);
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writel(fbi->regs.lcd_dccs, regs + REG_LCM_DCCS);
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}
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/*
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* Alters the hardware state.
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*
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*/
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static int nuc900fb_set_par(struct fb_info *info)
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{
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struct fb_var_screeninfo *var = &info->var;
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switch (var->bits_per_pixel) {
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case 32:
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case 24:
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case 18:
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case 16:
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case 12:
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info->fix.visual = FB_VISUAL_TRUECOLOR;
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break;
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case 1:
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info->fix.visual = FB_VISUAL_MONO01;
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break;
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default:
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
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break;
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}
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info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
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/* activate this new configuration */
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nuc900fb_activate_var(info);
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return 0;
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}
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static inline unsigned int chan_to_field(unsigned int chan,
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struct fb_bitfield *bf)
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{
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chan &= 0xffff;
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chan >>= 16 - bf->length;
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return chan << bf->offset;
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}
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static int nuc900fb_setcolreg(unsigned regno,
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unsigned red, unsigned green, unsigned blue,
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unsigned transp, struct fb_info *info)
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{
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unsigned int val;
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switch (info->fix.visual) {
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case FB_VISUAL_TRUECOLOR:
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/* true-colour, use pseuo-palette */
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if (regno < 16) {
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u32 *pal = info->pseudo_palette;
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val = chan_to_field(red, &info->var.red);
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val |= chan_to_field(green, &info->var.green);
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val |= chan_to_field(blue, &info->var.blue);
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pal[regno] = val;
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}
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break;
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default:
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return 1; /* unknown type */
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}
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return 0;
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}
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/**
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* nuc900fb_blank
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*
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*/
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static int nuc900fb_blank(int blank_mode, struct fb_info *info)
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{
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return 0;
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}
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static struct fb_ops nuc900fb_ops = {
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.owner = THIS_MODULE,
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.fb_check_var = nuc900fb_check_var,
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.fb_set_par = nuc900fb_set_par,
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.fb_blank = nuc900fb_blank,
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.fb_setcolreg = nuc900fb_setcolreg,
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.fb_fillrect = cfb_fillrect,
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.fb_copyarea = cfb_copyarea,
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.fb_imageblit = cfb_imageblit,
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};
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static inline void modify_gpio(void __iomem *reg,
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unsigned long set, unsigned long mask)
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{
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unsigned long tmp;
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tmp = readl(reg) & ~mask;
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writel(tmp | set, reg);
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}
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/*
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* Initialise LCD-related registers
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*/
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static int nuc900fb_init_registers(struct fb_info *info)
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{
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struct nuc900fb_info *fbi = info->par;
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struct nuc900fb_mach_info *mach_info = dev_get_platdata(fbi->dev);
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void __iomem *regs = fbi->io;
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/*reset the display engine*/
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writel(0, regs + REG_LCM_DCCS);
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writel(readl(regs + REG_LCM_DCCS) | LCM_DCCS_ENG_RST,
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regs + REG_LCM_DCCS);
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ndelay(100);
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writel(readl(regs + REG_LCM_DCCS) & (~LCM_DCCS_ENG_RST),
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regs + REG_LCM_DCCS);
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ndelay(100);
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writel(0, regs + REG_LCM_DEV_CTRL);
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/* config gpio output */
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modify_gpio(W90X900_VA_GPIO + 0x54, mach_info->gpio_dir,
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mach_info->gpio_dir_mask);
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modify_gpio(W90X900_VA_GPIO + 0x58, mach_info->gpio_data,
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mach_info->gpio_data_mask);
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return 0;
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}
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/*
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* Alloc the SDRAM region of NUC900 for the frame buffer.
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* The buffer should be a non-cached, non-buffered, memory region
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* to allow palette and pixel writes without flushing the cache.
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*/
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static int nuc900fb_map_video_memory(struct fb_info *info)
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{
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struct nuc900fb_info *fbi = info->par;
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dma_addr_t map_dma;
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unsigned long map_size = PAGE_ALIGN(info->fix.smem_len);
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dev_dbg(fbi->dev, "nuc900fb_map_video_memory(fbi=%p) map_size %lu\n",
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fbi, map_size);
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info->screen_base = dma_alloc_wc(fbi->dev, map_size, &map_dma,
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GFP_KERNEL);
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if (!info->screen_base)
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return -ENOMEM;
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memset(info->screen_base, 0x00, map_size);
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info->fix.smem_start = map_dma;
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return 0;
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}
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static inline void nuc900fb_unmap_video_memory(struct fb_info *info)
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{
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struct nuc900fb_info *fbi = info->par;
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dma_free_wc(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
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info->screen_base, info->fix.smem_start);
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}
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static irqreturn_t nuc900fb_irqhandler(int irq, void *dev_id)
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{
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struct nuc900fb_info *fbi = dev_id;
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void __iomem *regs = fbi->io;
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void __iomem *irq_base = fbi->irq_base;
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unsigned long lcdirq = readl(regs + REG_LCM_INT_CS);
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if (lcdirq & LCM_INT_CS_DISP_F_STATUS) {
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writel(readl(irq_base) | 1<<30, irq_base);
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/* wait VA_EN low */
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if ((readl(regs + REG_LCM_DCCS) &
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LCM_DCCS_SINGLE) == LCM_DCCS_SINGLE)
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while ((readl(regs + REG_LCM_DCCS) &
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LCM_DCCS_VA_EN) == LCM_DCCS_VA_EN)
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;
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/* display_out-enable */
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writel(readl(regs + REG_LCM_DCCS) | LCM_DCCS_DISP_OUT_EN,
|
|
regs + REG_LCM_DCCS);
|
|
/* va-enable*/
|
|
writel(readl(regs + REG_LCM_DCCS) | LCM_DCCS_VA_EN,
|
|
regs + REG_LCM_DCCS);
|
|
} else if (lcdirq & LCM_INT_CS_UNDERRUN_INT) {
|
|
writel(readl(irq_base) | LCM_INT_CS_UNDERRUN_INT, irq_base);
|
|
} else if (lcdirq & LCM_INT_CS_BUS_ERROR_INT) {
|
|
writel(readl(irq_base) | LCM_INT_CS_BUS_ERROR_INT, irq_base);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
|
|
static int nuc900fb_cpufreq_transition(struct notifier_block *nb,
|
|
unsigned long val, void *data)
|
|
{
|
|
struct nuc900fb_info *info;
|
|
struct fb_info *fbinfo;
|
|
long delta_f;
|
|
info = container_of(nb, struct nuc900fb_info, freq_transition);
|
|
fbinfo = platform_get_drvdata(to_platform_device(info->dev));
|
|
|
|
delta_f = info->clk_rate - clk_get_rate(info->clk);
|
|
|
|
if ((val == CPUFREQ_POSTCHANGE && delta_f > 0) ||
|
|
(val == CPUFREQ_PRECHANGE && delta_f < 0)) {
|
|
info->clk_rate = clk_get_rate(info->clk);
|
|
nuc900fb_activate_var(fbinfo);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline int nuc900fb_cpufreq_register(struct nuc900fb_info *fbi)
|
|
{
|
|
fbi->freq_transition.notifier_call = nuc900fb_cpufreq_transition;
|
|
return cpufreq_register_notifier(&fbi->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
|
|
static inline void nuc900fb_cpufreq_deregister(struct nuc900fb_info *fbi)
|
|
{
|
|
cpufreq_unregister_notifier(&fbi->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
#else
|
|
static inline int nuc900fb_cpufreq_transition(struct notifier_block *nb,
|
|
unsigned long val, void *data)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int nuc900fb_cpufreq_register(struct nuc900fb_info *fbi)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void nuc900fb_cpufreq_deregister(struct nuc900fb_info *info)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
static char driver_name[] = "nuc900fb";
|
|
|
|
static int nuc900fb_probe(struct platform_device *pdev)
|
|
{
|
|
struct nuc900fb_info *fbi;
|
|
struct nuc900fb_display *display;
|
|
struct fb_info *fbinfo;
|
|
struct nuc900fb_mach_info *mach_info;
|
|
struct resource *res;
|
|
int ret;
|
|
int irq;
|
|
int i;
|
|
int size;
|
|
|
|
dev_dbg(&pdev->dev, "devinit\n");
|
|
mach_info = dev_get_platdata(&pdev->dev);
|
|
if (mach_info == NULL) {
|
|
dev_err(&pdev->dev,
|
|
"no platform data for lcd, cannot attach\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (mach_info->default_display > mach_info->num_displays) {
|
|
dev_err(&pdev->dev,
|
|
"default display No. is %d but only %d displays \n",
|
|
mach_info->default_display, mach_info->num_displays);
|
|
return -EINVAL;
|
|
}
|
|
|
|
|
|
display = mach_info->displays + mach_info->default_display;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "no irq for device\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
fbinfo = framebuffer_alloc(sizeof(struct nuc900fb_info), &pdev->dev);
|
|
if (!fbinfo)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, fbinfo);
|
|
|
|
fbi = fbinfo->par;
|
|
fbi->dev = &pdev->dev;
|
|
|
|
#ifdef CONFIG_CPU_NUC950
|
|
fbi->drv_type = LCDDRV_NUC950;
|
|
#endif
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
size = resource_size(res);
|
|
fbi->mem = request_mem_region(res->start, size, pdev->name);
|
|
if (fbi->mem == NULL) {
|
|
dev_err(&pdev->dev, "failed to alloc memory region\n");
|
|
ret = -ENOENT;
|
|
goto free_fb;
|
|
}
|
|
|
|
fbi->io = ioremap(res->start, size);
|
|
if (fbi->io == NULL) {
|
|
dev_err(&pdev->dev, "ioremap() of lcd registers failed\n");
|
|
ret = -ENXIO;
|
|
goto release_mem_region;
|
|
}
|
|
|
|
fbi->irq_base = fbi->io + REG_LCM_INT_CS;
|
|
|
|
|
|
/* Stop the LCD */
|
|
writel(0, fbi->io + REG_LCM_DCCS);
|
|
|
|
/* fill the fbinfo*/
|
|
strcpy(fbinfo->fix.id, driver_name);
|
|
fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
|
|
fbinfo->fix.type_aux = 0;
|
|
fbinfo->fix.xpanstep = 0;
|
|
fbinfo->fix.ypanstep = 0;
|
|
fbinfo->fix.ywrapstep = 0;
|
|
fbinfo->fix.accel = FB_ACCEL_NONE;
|
|
fbinfo->var.nonstd = 0;
|
|
fbinfo->var.activate = FB_ACTIVATE_NOW;
|
|
fbinfo->var.accel_flags = 0;
|
|
fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
|
|
fbinfo->fbops = &nuc900fb_ops;
|
|
fbinfo->flags = FBINFO_FLAG_DEFAULT;
|
|
fbinfo->pseudo_palette = &fbi->pseudo_pal;
|
|
|
|
ret = request_irq(irq, nuc900fb_irqhandler, 0, pdev->name, fbi);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "cannot register irq handler %d -err %d\n",
|
|
irq, ret);
|
|
ret = -EBUSY;
|
|
goto release_regs;
|
|
}
|
|
|
|
fbi->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(fbi->clk)) {
|
|
printk(KERN_ERR "nuc900-lcd:failed to get lcd clock source\n");
|
|
ret = PTR_ERR(fbi->clk);
|
|
goto release_irq;
|
|
}
|
|
|
|
clk_enable(fbi->clk);
|
|
dev_dbg(&pdev->dev, "got and enabled clock\n");
|
|
|
|
fbi->clk_rate = clk_get_rate(fbi->clk);
|
|
|
|
/* calutate the video buffer size */
|
|
for (i = 0; i < mach_info->num_displays; i++) {
|
|
unsigned long smem_len = mach_info->displays[i].xres;
|
|
smem_len *= mach_info->displays[i].yres;
|
|
smem_len *= mach_info->displays[i].bpp;
|
|
smem_len >>= 3;
|
|
if (fbinfo->fix.smem_len < smem_len)
|
|
fbinfo->fix.smem_len = smem_len;
|
|
}
|
|
|
|
/* Initialize Video Memory */
|
|
ret = nuc900fb_map_video_memory(fbinfo);
|
|
if (ret) {
|
|
printk(KERN_ERR "Failed to allocate video RAM: %x\n", ret);
|
|
goto release_clock;
|
|
}
|
|
|
|
dev_dbg(&pdev->dev, "got video memory\n");
|
|
|
|
fbinfo->var.xres = display->xres;
|
|
fbinfo->var.yres = display->yres;
|
|
fbinfo->var.bits_per_pixel = display->bpp;
|
|
|
|
nuc900fb_init_registers(fbinfo);
|
|
|
|
nuc900fb_check_var(&fbinfo->var, fbinfo);
|
|
|
|
ret = nuc900fb_cpufreq_register(fbi);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to register cpufreq\n");
|
|
goto free_video_memory;
|
|
}
|
|
|
|
ret = register_framebuffer(fbinfo);
|
|
if (ret) {
|
|
printk(KERN_ERR "failed to register framebuffer device: %d\n",
|
|
ret);
|
|
goto free_cpufreq;
|
|
}
|
|
|
|
fb_info(fbinfo, "%s frame buffer device\n", fbinfo->fix.id);
|
|
|
|
return 0;
|
|
|
|
free_cpufreq:
|
|
nuc900fb_cpufreq_deregister(fbi);
|
|
free_video_memory:
|
|
nuc900fb_unmap_video_memory(fbinfo);
|
|
release_clock:
|
|
clk_disable(fbi->clk);
|
|
clk_put(fbi->clk);
|
|
release_irq:
|
|
free_irq(irq, fbi);
|
|
release_regs:
|
|
iounmap(fbi->io);
|
|
release_mem_region:
|
|
release_mem_region(res->start, size);
|
|
free_fb:
|
|
framebuffer_release(fbinfo);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* shutdown the lcd controller
|
|
*/
|
|
static void nuc900fb_stop_lcd(struct fb_info *info)
|
|
{
|
|
struct nuc900fb_info *fbi = info->par;
|
|
void __iomem *regs = fbi->io;
|
|
|
|
writel((~LCM_DCCS_DISP_INT_EN) | (~LCM_DCCS_VA_EN) | (~LCM_DCCS_OSD_EN),
|
|
regs + REG_LCM_DCCS);
|
|
}
|
|
|
|
/*
|
|
* Cleanup
|
|
*/
|
|
static int nuc900fb_remove(struct platform_device *pdev)
|
|
{
|
|
struct fb_info *fbinfo = platform_get_drvdata(pdev);
|
|
struct nuc900fb_info *fbi = fbinfo->par;
|
|
int irq;
|
|
|
|
nuc900fb_stop_lcd(fbinfo);
|
|
msleep(1);
|
|
|
|
unregister_framebuffer(fbinfo);
|
|
nuc900fb_cpufreq_deregister(fbi);
|
|
nuc900fb_unmap_video_memory(fbinfo);
|
|
|
|
iounmap(fbi->io);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
free_irq(irq, fbi);
|
|
|
|
release_resource(fbi->mem);
|
|
kfree(fbi->mem);
|
|
|
|
framebuffer_release(fbinfo);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
/*
|
|
* suspend and resume support for the lcd controller
|
|
*/
|
|
|
|
static int nuc900fb_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct fb_info *fbinfo = platform_get_drvdata(dev);
|
|
struct nuc900fb_info *info = fbinfo->par;
|
|
|
|
nuc900fb_stop_lcd(fbinfo);
|
|
msleep(1);
|
|
clk_disable(info->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int nuc900fb_resume(struct platform_device *dev)
|
|
{
|
|
struct fb_info *fbinfo = platform_get_drvdata(dev);
|
|
struct nuc900fb_info *fbi = fbinfo->par;
|
|
|
|
printk(KERN_INFO "nuc900fb resume\n");
|
|
|
|
clk_enable(fbi->clk);
|
|
msleep(1);
|
|
|
|
nuc900fb_init_registers(fbinfo);
|
|
nuc900fb_activate_var(fbinfo);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define nuc900fb_suspend NULL
|
|
#define nuc900fb_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver nuc900fb_driver = {
|
|
.probe = nuc900fb_probe,
|
|
.remove = nuc900fb_remove,
|
|
.suspend = nuc900fb_suspend,
|
|
.resume = nuc900fb_resume,
|
|
.driver = {
|
|
.name = "nuc900-lcd",
|
|
},
|
|
};
|
|
|
|
module_platform_driver(nuc900fb_driver);
|
|
|
|
MODULE_DESCRIPTION("Framebuffer driver for the NUC900");
|
|
MODULE_LICENSE("GPL");
|