183 lines
6.2 KiB
C
183 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2010 Juergen Beisert, Pengutronix
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* Copyright (C) 2016 Marek Vasut <marex@denx.de>
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*
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* i.MX23/i.MX28/i.MX6SX MXSFB LCD controller driver.
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*/
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#ifndef __MXSFB_REGS_H__
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#define __MXSFB_REGS_H__
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#define REG_SET 4
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#define REG_CLR 8
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#define LCDC_CTRL 0x00
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#define LCDC_CTRL1 0x10
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#define LCDC_V4_CTRL2 0x20
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#define LCDC_V3_TRANSFER_COUNT 0x20
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#define LCDC_V4_TRANSFER_COUNT 0x30
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#define LCDC_V4_CUR_BUF 0x40
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#define LCDC_V4_NEXT_BUF 0x50
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#define LCDC_V3_CUR_BUF 0x30
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#define LCDC_V3_NEXT_BUF 0x40
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#define LCDC_TIMING 0x60
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#define LCDC_VDCTRL0 0x70
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#define LCDC_VDCTRL1 0x80
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#define LCDC_VDCTRL2 0x90
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#define LCDC_VDCTRL3 0xa0
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#define LCDC_VDCTRL4 0xb0
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#define LCDC_DVICTRL0 0xc0
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#define LCDC_DVICTRL1 0xd0
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#define LCDC_DVICTRL2 0xe0
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#define LCDC_DVICTRL3 0xf0
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#define LCDC_DVICTRL4 0x100
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#define LCDC_V4_DATA 0x180
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#define LCDC_V3_DATA 0x1b0
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#define LCDC_V4_DEBUG0 0x1d0
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#define LCDC_V3_DEBUG0 0x1f0
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#define LCDC_AS_CTRL 0x210
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#define LCDC_AS_BUF 0x220
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#define LCDC_AS_NEXT_BUF 0x230
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/* reg bit manipulation */
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#define REG_PUT(x, h, l) (((x) << (l)) & GENMASK(h, l))
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#define REG_GET(x, h, l) (((x) & GENMASK(h, l)) >> (l))
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#define SWIZZLE_LE 0 /* Little-Endian or No swap */
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#define SWIZZLE_BE 1 /* Big-Endian or swap all */
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#define SWIZZLE_HWD 2 /* Swap half-words */
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#define SWIZZLE_HWD_BYTE 3 /* Swap bytes within each half-word */
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#define CTRL_SFTRST BIT(31)
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#define CTRL_CLKGATE BIT(30)
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#define CTRL_SHIFT_DIR(x) REG_PUT((x), 26, 26)
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#define CTRL_SHIFT_NUM(x) REG_PUT((x), 25, 21)
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#define CTRL_BYPASS_COUNT BIT(19)
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#define CTRL_VSYNC_MODE BIT(18)
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#define CTRL_DOTCLK_MODE BIT(17)
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#define CTRL_DATA_SELECT BIT(16)
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#define CTRL_INPUT_SWIZZLE(x) REG_PUT((x), 15, 14)
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#define CTRL_CSC_SWIZZLE(x) REG_PUT((x), 13, 12)
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#define CTRL_SET_BUS_WIDTH(x) REG_PUT((x), 11, 10)
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#define CTRL_GET_BUS_WIDTH(x) REG_GET((x), 11, 10)
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#define CTRL_BUS_WIDTH_MASK REG_PUT((0x3), 11, 10)
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#define CTRL_SET_WORD_LENGTH(x) REG_PUT((x), 9, 8)
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#define CTRL_GET_WORD_LENGTH(x) REG_GET((x), 9, 8)
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#define CTRL_MASTER BIT(5)
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#define CTRL_DF16 BIT(3)
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#define CTRL_DF18 BIT(2)
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#define CTRL_DF24 BIT(1)
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#define CTRL_RUN BIT(0)
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#define CTRL1_RECOVERY_ON_UNDERFLOW BIT(24)
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#define CTRL1_FIFO_CLEAR BIT(21)
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/*
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* BYTE_PACKAGING
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*
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* This bitfield is used to show which data bytes in a 32-bit word area valid.
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* Default value 0xf indicates that all bytes are valid. For 8-bit transfers,
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* any combination in this bitfield will mean valid data is present in the
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* corresponding bytes. In the 16-bit mode, a 16-bit half-word is valid only if
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* adjacent bits [1:0] or [3:2] or both are 1. A value of 0x0 will mean that
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* none of the bytes are valid and should not be used. For example, set the bit
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* field value to 0x7 if the display data is arranged in the 24-bit unpacked
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* format (A-R-G-B where A value does not have be transmitted).
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*/
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#define CTRL1_SET_BYTE_PACKAGING(x) REG_PUT((x), 19, 16)
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#define CTRL1_GET_BYTE_PACKAGING(x) REG_GET((x), 19, 16)
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#define CTRL1_CUR_FRAME_DONE_IRQ_EN BIT(13)
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#define CTRL1_CUR_FRAME_DONE_IRQ BIT(9)
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#define CTRL2_OUTSTANDING_REQS(x) REG_PUT((x), 23, 21)
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#define REQ_1 0
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#define REQ_2 1
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#define REQ_4 2
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#define REQ_8 3
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#define REQ_16 4
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#define CTRL2_ODD_LINE_PATTERN(x) REG_PUT((x), 18, 16)
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#define CTRL2_EVEN_LINE_PATTERN(x) REG_PUT((x), 14, 12)
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#define CTRL2_LINE_PATTERN_RGB 0
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#define CTRL2_LINE_PATTERN_RBG 1
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#define CTRL2_LINE_PATTERN_GBR 2
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#define CTRL2_LINE_PATTERN_GRB 3
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#define CTRL2_LINE_PATTERN_BRG 4
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#define CTRL2_LINE_PATTERN_BGR 5
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#define CTRL2_LINE_PATTERN_CLR 7
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#define CTRL2_LCD_RESET BIT(0)
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#define TRANSFER_COUNT_SET_VCOUNT(x) REG_PUT((x), 31, 16)
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#define TRANSFER_COUNT_GET_VCOUNT(x) REG_GET((x), 31, 16)
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#define TRANSFER_COUNT_SET_HCOUNT(x) REG_PUT((x), 15, 0)
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#define TRANSFER_COUNT_GET_HCOUNT(x) REG_GET((x), 15, 0)
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#define VDCTRL0_ENABLE_PRESENT BIT(28)
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#define VDCTRL0_VSYNC_ACT_HIGH BIT(27)
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#define VDCTRL0_HSYNC_ACT_HIGH BIT(26)
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#define VDCTRL0_DOTCLK_ACT_FALLING BIT(25)
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#define VDCTRL0_ENABLE_ACT_HIGH BIT(24)
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#define VDCTRL0_VSYNC_PERIOD_UNIT BIT(21)
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#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT BIT(20)
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#define VDCTRL0_HALF_LINE BIT(19)
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#define VDCTRL0_HALF_LINE_MODE BIT(18)
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#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) REG_PUT((x), 17, 0)
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#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) REG_GET((x), 17, 0)
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#define VDCTRL2_SET_HSYNC_PERIOD(x) REG_PUT((x), 15, 0)
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#define VDCTRL2_GET_HSYNC_PERIOD(x) REG_GET((x), 15, 0)
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#define VDCTRL3_MUX_SYNC_SIGNALS BIT(29)
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#define VDCTRL3_VSYNC_ONLY BIT(28)
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#define SET_HOR_WAIT_CNT(x) REG_PUT((x), 27, 16)
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#define GET_HOR_WAIT_CNT(x) REG_GET((x), 27, 16)
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#define SET_VERT_WAIT_CNT(x) REG_PUT((x), 15, 0)
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#define GET_VERT_WAIT_CNT(x) REG_GET((x), 15, 0)
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#define VDCTRL4_SET_DOTCLK_DLY(x) REG_PUT((x), 31, 29) /* v4 only */
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#define VDCTRL4_GET_DOTCLK_DLY(x) REG_GET((x), 31, 29) /* v4 only */
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#define VDCTRL4_SYNC_SIGNALS_ON BIT(18)
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#define SET_DOTCLK_H_VALID_DATA_CNT(x) REG_PUT((x), 17, 0)
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#define DEBUG0_HSYNC BIT(26)
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#define DEBUG0_VSYNC BIT(25)
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/* pigeon registers for crop */
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#define HW_EPDC_PIGEON_12_0 0xb00
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#define HW_EPDC_PIGEON_12_1 0xb10
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#define HW_EPDC_PIGEON_12_2 0xb20
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#define PIGEON_12_0_SET_STATE_MASK(x) REG_PUT((x), 31, 24)
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#define PIGEON_12_0_SET_MASK_CNT(x) REG_PUT((x), 23, 12)
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#define PIGEON_12_0_SET_MASK_CNT_SEL(x) REG_PUT((x), 11, 8)
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#define PIGEON_12_0_SET_OFFSET(x) REG_PUT((x), 7, 4)
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#define PIGEON_12_0_SET_INC_SEL(x) REG_PUT((x), 3, 2)
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#define PIGEON_12_0_POL_ACTIVE_LOW BIT(1)
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#define PIGEON_12_0_EN BIT(0)
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#define PIGEON_12_1_SET_CLR_CNT(x) REG_PUT((x), 31, 16)
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#define PIGEON_12_1_SET_SET_CNT(x) REG_PUT((x), 15, 0)
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#define MXSFB_MIN_XRES 120
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#define MXSFB_MIN_YRES 120
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#define MXSFB_MAX_XRES 0xffff
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#define MXSFB_MAX_YRES 0xffff
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#define RED 0
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#define GREEN 1
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#define BLUE 2
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#define TRANSP 3
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#define STMLCDIF_8BIT 1 /* pixel data bus to the display is of 8 bit width */
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#define STMLCDIF_16BIT 0 /* pixel data bus to the display is of 16 bit width */
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#define STMLCDIF_18BIT 2 /* pixel data bus to the display is of 18 bit width */
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#define STMLCDIF_24BIT 3 /* pixel data bus to the display is of 24 bit width */
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#define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT BIT(6)
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#define MXSFB_SYNC_DOTCLK_FALLING_ACT BIT(7) /* negative edge sampling */
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#endif /* __MXSFB_REGS_H__ */
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