51bc620ba9
This patch adds support for DWARF register mappings and libdw registers initialization, which is used by perf callchain analyzing when --call-graph=dwarf is given. Signed-off-by: Mao Han <han_mao@c-sky.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Greentime Hu <green.hu@gmail.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: linux-riscv <linux-riscv@lists.infradead.org> Cc: Christoph Hellwig <hch@lst.de> Cc: Guo Ren <guoren@kernel.org> Tested-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
43 lines
920 B
C
43 lines
920 B
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/* Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. */
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#ifndef _ASM_RISCV_PERF_REGS_H
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#define _ASM_RISCV_PERF_REGS_H
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enum perf_event_riscv_regs {
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PERF_REG_RISCV_PC,
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PERF_REG_RISCV_RA,
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PERF_REG_RISCV_SP,
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PERF_REG_RISCV_GP,
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PERF_REG_RISCV_TP,
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PERF_REG_RISCV_T0,
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PERF_REG_RISCV_T1,
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PERF_REG_RISCV_T2,
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PERF_REG_RISCV_S0,
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PERF_REG_RISCV_S1,
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PERF_REG_RISCV_A0,
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PERF_REG_RISCV_A1,
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PERF_REG_RISCV_A2,
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PERF_REG_RISCV_A3,
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PERF_REG_RISCV_A4,
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PERF_REG_RISCV_A5,
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PERF_REG_RISCV_A6,
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PERF_REG_RISCV_A7,
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PERF_REG_RISCV_S2,
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PERF_REG_RISCV_S3,
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PERF_REG_RISCV_S4,
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PERF_REG_RISCV_S5,
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PERF_REG_RISCV_S6,
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PERF_REG_RISCV_S7,
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PERF_REG_RISCV_S8,
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PERF_REG_RISCV_S9,
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PERF_REG_RISCV_S10,
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PERF_REG_RISCV_S11,
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PERF_REG_RISCV_T3,
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PERF_REG_RISCV_T4,
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PERF_REG_RISCV_T5,
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PERF_REG_RISCV_T6,
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PERF_REG_RISCV_MAX,
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};
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#endif /* _ASM_RISCV_PERF_REGS_H */
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