Catalin Marinas 35a8697692 arm64: Update the TCR_EL1 translation granule definitions for 16K pages ... The current TCR register setting in arch/arm64/mm/proc.S assumes that TCR_EL1.TG* fields are one bit wide and bit 31 is RES1 (reserved, set to 1). With the addition of 16K pages (currently unsupported in the kernel), the TCR_EL1.TG* fields have been extended to two bits. This patch updates the corresponding Linux definitions and drops the bit 31 setting in proc.S in favour of the new macros. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Joe Sylve <joe.sylve@gmail.com>		2014-04-03 10:43:11 +01:00
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cache.S	arm64: remove unnecessary cache flush at boot	2014-03-04 01:07:22 +00:00
context.c	arm64: Process management	2012-09-17 13:41:58 +01:00
copypage.c
dma-mapping.c	arm64: Remove pgprot_dmacoherent()	2014-03-24 10:35:35 +00:00
extable.c
fault.c	arm64: Make do_bad_area() function static	2013-09-20 09:56:05 +01:00
flush.c	arm64: Remove __flush_dcache_page()	2013-06-07 17:58:30 +01:00
hugetlbpage.c	mm: migrate: check movability of hugepage in unmap_and_move_huge_page()	2013-09-11 15:57:49 -07:00
init.c	arm64: Use swiotlb late initialisation	2014-02-27 14:11:53 +00:00
ioremap.c	arm64: allow ioremap_cache() to use existing RAM mappings	2013-10-30 12:10:37 +00:00
Makefile	ARM64: mm: HugeTLB support.	2013-06-14 09:52:40 +01:00
mm.h	arm64: Remove __flush_dcache_page()	2013-06-07 17:58:30 +01:00
mmap.c	mm: remove free_area_cache	2013-07-10 18:11:34 -07:00
mmu.c	arm64: Invalidate the TLB when replacing pmd entries during boot	2014-02-05 10:30:51 +00:00
pgd.c	arm64: simplify pgd_alloc	2014-02-05 10:45:07 +00:00
proc-macros.S	arm64: mm: use ubfm for dcache_line_size	2014-01-22 16:23:58 +00:00
proc.S	arm64: Update the TCR_EL1 translation granule definitions for 16K pages	2014-04-03 10:43:11 +01:00
tlb.S	arm64: use correct register width when retrieving ASID	2013-09-25 16:42:23 +01:00