1a64634255
It'd be pretty awesome if someone would care enough to port this all properly to a class interface, perhaps submitting a command stream to the core via a sw object on PFIFO (emulating how EVO works basically, and also what nvidia have done forever..).. But, this seems unlikely given how old this hardware is now, so, lets just hide it away. There's a heap of other bits and pieces laying around that are still tangled. I'll (re)move them in pieces. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
71 lines
2.1 KiB
C
71 lines
2.1 KiB
C
#include <drm/drmP.h>
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#include <drm/drm_mode.h>
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#include "nouveau_drm.h"
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#include "nouveau_reg.h"
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#include "nouveau_crtc.h"
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#include "hw.h"
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static void
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nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
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{
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nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true);
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}
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static void
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nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
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{
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nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false);
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}
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static void
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nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
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{
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nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y;
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NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index,
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NV_PRAMDAC_CU_START_POS,
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XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) |
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XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X));
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}
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static void
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crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
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{
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NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
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crtcstate->CRTC[index]);
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}
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static void
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nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
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{
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struct drm_device *dev = nv_crtc->base.dev;
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
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struct drm_crtc *crtc = &nv_crtc->base;
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regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
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MASK(NV_CIO_CRE_HCUR_ASI) |
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XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR);
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regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
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XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR);
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if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
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regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
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MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
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regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24;
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
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if (nv_device(drm->device)->card_type == NV_40)
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nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
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}
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int
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nv04_cursor_init(struct nouveau_crtc *crtc)
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{
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crtc->cursor.set_offset = nv04_cursor_set_offset;
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crtc->cursor.set_pos = nv04_cursor_set_pos;
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crtc->cursor.hide = nv04_cursor_hide;
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crtc->cursor.show = nv04_cursor_show;
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return 0;
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}
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