![Frederic Barrat](/assets/img/avatar_default.png)
Some of the functions done by the generic driver should also be needed by other opencapi drivers: attaching a context to an adapter, translation fault handling, AFU interrupt allocation... So to avoid code duplication, the driver provides a kernel API that other drivers can use, similar to calling a in-kernel library. It is still a bit theoretical, for lack of real hardware, and will likely need adjustements down the road. But we used the cxlflash driver as a guinea pig. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
724 lines
18 KiB
C
724 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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// Copyright 2017 IBM Corp.
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#include <linux/pci.h>
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#include <asm/pnv-ocxl.h>
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#include <misc/ocxl.h>
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#include <misc/ocxl-config.h>
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#define EXTRACT_BIT(val, bit) (!!(val & BIT(bit)))
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#define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
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#define OCXL_DVSEC_AFU_IDX_MASK GENMASK(5, 0)
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#define OCXL_DVSEC_ACTAG_MASK GENMASK(11, 0)
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#define OCXL_DVSEC_PASID_MASK GENMASK(19, 0)
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#define OCXL_DVSEC_PASID_LOG_MASK GENMASK(4, 0)
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#define OCXL_DVSEC_TEMPL_VERSION 0x0
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#define OCXL_DVSEC_TEMPL_NAME 0x4
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#define OCXL_DVSEC_TEMPL_AFU_VERSION 0x1C
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#define OCXL_DVSEC_TEMPL_MMIO_GLOBAL 0x20
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#define OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ 0x28
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#define OCXL_DVSEC_TEMPL_MMIO_PP 0x30
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#define OCXL_DVSEC_TEMPL_MMIO_PP_SZ 0x38
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#define OCXL_DVSEC_TEMPL_MEM_SZ 0x3C
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#define OCXL_DVSEC_TEMPL_WWID 0x40
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#define OCXL_MAX_AFU_PER_FUNCTION 64
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#define OCXL_TEMPL_LEN 0x58
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#define OCXL_TEMPL_NAME_LEN 24
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#define OCXL_CFG_TIMEOUT 3
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static int find_dvsec(struct pci_dev *dev, int dvsec_id)
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{
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int vsec = 0;
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u16 vendor, id;
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while ((vsec = pci_find_next_ext_capability(dev, vsec,
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OCXL_EXT_CAP_ID_DVSEC))) {
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pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
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&vendor);
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pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
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if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id)
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return vsec;
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}
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return 0;
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}
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static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
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{
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int vsec = 0;
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u16 vendor, id;
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u8 idx;
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while ((vsec = pci_find_next_ext_capability(dev, vsec,
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OCXL_EXT_CAP_ID_DVSEC))) {
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pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
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&vendor);
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pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
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if (vendor == PCI_VENDOR_ID_IBM &&
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id == OCXL_DVSEC_AFU_CTRL_ID) {
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pci_read_config_byte(dev,
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vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX,
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&idx);
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if (idx == afu_idx)
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return vsec;
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}
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}
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return 0;
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}
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static int read_pasid(struct pci_dev *dev, struct ocxl_fn_config *fn)
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{
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u16 val;
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int pos;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PASID);
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if (!pos) {
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/*
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* PASID capability is not mandatory, but there
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* shouldn't be any AFU
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*/
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dev_dbg(&dev->dev, "Function doesn't require any PASID\n");
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fn->max_pasid_log = -1;
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goto out;
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}
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pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
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fn->max_pasid_log = EXTRACT_BITS(val, 8, 12);
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out:
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dev_dbg(&dev->dev, "PASID capability:\n");
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dev_dbg(&dev->dev, " Max PASID log = %d\n", fn->max_pasid_log);
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return 0;
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}
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static int read_dvsec_tl(struct pci_dev *dev, struct ocxl_fn_config *fn)
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{
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int pos;
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pos = find_dvsec(dev, OCXL_DVSEC_TL_ID);
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if (!pos && PCI_FUNC(dev->devfn) == 0) {
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dev_err(&dev->dev, "Can't find TL DVSEC\n");
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return -ENODEV;
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}
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if (pos && PCI_FUNC(dev->devfn) != 0) {
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dev_err(&dev->dev, "TL DVSEC is only allowed on function 0\n");
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return -ENODEV;
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}
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fn->dvsec_tl_pos = pos;
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return 0;
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}
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static int read_dvsec_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
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{
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int pos, afu_present;
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u32 val;
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pos = find_dvsec(dev, OCXL_DVSEC_FUNC_ID);
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if (!pos) {
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dev_err(&dev->dev, "Can't find function DVSEC\n");
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return -ENODEV;
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}
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fn->dvsec_function_pos = pos;
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pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
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afu_present = EXTRACT_BIT(val, 31);
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if (!afu_present) {
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fn->max_afu_index = -1;
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dev_dbg(&dev->dev, "Function doesn't define any AFU\n");
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goto out;
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}
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fn->max_afu_index = EXTRACT_BITS(val, 24, 29);
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out:
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dev_dbg(&dev->dev, "Function DVSEC:\n");
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dev_dbg(&dev->dev, " Max AFU index = %d\n", fn->max_afu_index);
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return 0;
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}
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static int read_dvsec_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn)
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{
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int pos;
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if (fn->max_afu_index < 0) {
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fn->dvsec_afu_info_pos = -1;
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return 0;
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}
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pos = find_dvsec(dev, OCXL_DVSEC_AFU_INFO_ID);
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if (!pos) {
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dev_err(&dev->dev, "Can't find AFU information DVSEC\n");
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return -ENODEV;
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}
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fn->dvsec_afu_info_pos = pos;
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return 0;
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}
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static int read_dvsec_vendor(struct pci_dev *dev)
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{
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int pos;
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u32 cfg, tlx, dlx;
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/*
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* vendor specific DVSEC is optional
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*
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* It's currently only used on function 0 to specify the
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* version of some logic blocks. Some older images may not
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* even have it so we ignore any errors
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*/
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if (PCI_FUNC(dev->devfn) != 0)
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return 0;
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pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
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if (!pos)
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return 0;
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pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_CFG_VERS, &cfg);
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pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_TLX_VERS, &tlx);
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pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_DLX_VERS, &dlx);
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dev_dbg(&dev->dev, "Vendor specific DVSEC:\n");
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dev_dbg(&dev->dev, " CFG version = 0x%x\n", cfg);
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dev_dbg(&dev->dev, " TLX version = 0x%x\n", tlx);
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dev_dbg(&dev->dev, " DLX version = 0x%x\n", dlx);
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return 0;
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}
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static int validate_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
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{
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if (fn->max_pasid_log == -1 && fn->max_afu_index >= 0) {
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dev_err(&dev->dev,
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"AFUs are defined but no PASIDs are requested\n");
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return -EINVAL;
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}
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if (fn->max_afu_index > OCXL_MAX_AFU_PER_FUNCTION) {
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dev_err(&dev->dev,
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"Max AFU index out of architectural limit (%d vs %d)\n",
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fn->max_afu_index, OCXL_MAX_AFU_PER_FUNCTION);
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return -EINVAL;
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}
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return 0;
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}
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int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
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{
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int rc;
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rc = read_pasid(dev, fn);
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if (rc) {
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dev_err(&dev->dev, "Invalid PASID configuration: %d\n", rc);
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return -ENODEV;
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}
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rc = read_dvsec_tl(dev, fn);
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if (rc) {
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dev_err(&dev->dev,
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"Invalid Transaction Layer DVSEC configuration: %d\n",
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rc);
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return -ENODEV;
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}
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rc = read_dvsec_function(dev, fn);
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if (rc) {
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dev_err(&dev->dev,
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"Invalid Function DVSEC configuration: %d\n", rc);
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return -ENODEV;
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}
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rc = read_dvsec_afu_info(dev, fn);
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if (rc) {
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dev_err(&dev->dev, "Invalid AFU configuration: %d\n", rc);
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return -ENODEV;
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}
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rc = read_dvsec_vendor(dev);
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if (rc) {
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dev_err(&dev->dev,
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"Invalid vendor specific DVSEC configuration: %d\n",
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rc);
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return -ENODEV;
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}
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rc = validate_function(dev, fn);
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return rc;
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}
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EXPORT_SYMBOL_GPL(ocxl_config_read_function);
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static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn,
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int offset, u32 *data)
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{
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u32 val;
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unsigned long timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
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int pos = fn->dvsec_afu_info_pos;
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/* Protect 'data valid' bit */
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if (EXTRACT_BIT(offset, 31)) {
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dev_err(&dev->dev, "Invalid offset in AFU info DVSEC\n");
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return -EINVAL;
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}
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pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, offset);
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pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
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while (!EXTRACT_BIT(val, 31)) {
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if (time_after_eq(jiffies, timeout)) {
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dev_err(&dev->dev,
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"Timeout while reading AFU info DVSEC (offset=%d)\n",
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offset);
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return -EBUSY;
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}
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cpu_relax();
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pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
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}
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pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_DATA, data);
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return 0;
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}
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int ocxl_config_check_afu_index(struct pci_dev *dev,
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struct ocxl_fn_config *fn, int afu_idx)
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{
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u32 val;
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int rc, templ_major, templ_minor, len;
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pci_write_config_word(dev, fn->dvsec_afu_info_pos, afu_idx);
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rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val);
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if (rc)
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return rc;
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/* AFU index map can have holes */
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if (!val)
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return 0;
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templ_major = EXTRACT_BITS(val, 8, 15);
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templ_minor = EXTRACT_BITS(val, 0, 7);
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dev_dbg(&dev->dev, "AFU descriptor template version %d.%d\n",
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templ_major, templ_minor);
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len = EXTRACT_BITS(val, 16, 31);
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if (len != OCXL_TEMPL_LEN) {
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dev_warn(&dev->dev,
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"Unexpected template length in AFU information (%#x)\n",
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len);
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}
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return 1;
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}
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EXPORT_SYMBOL_GPL(ocxl_config_check_afu_index);
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static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn,
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struct ocxl_afu_config *afu)
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{
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int i, rc;
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u32 val, *ptr;
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BUILD_BUG_ON(OCXL_AFU_NAME_SZ < OCXL_TEMPL_NAME_LEN);
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for (i = 0; i < OCXL_TEMPL_NAME_LEN; i += 4) {
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rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
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if (rc)
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return rc;
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ptr = (u32 *) &afu->name[i];
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*ptr = val;
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}
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afu->name[OCXL_AFU_NAME_SZ - 1] = '\0'; /* play safe */
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return 0;
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}
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static int read_afu_mmio(struct pci_dev *dev, struct ocxl_fn_config *fn,
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struct ocxl_afu_config *afu)
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{
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int rc;
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u32 val;
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/*
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* Global MMIO
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*/
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rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
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if (rc)
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return rc;
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afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2);
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afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
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rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
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if (rc)
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return rc;
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afu->global_mmio_offset += (u64) val << 32;
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rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
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if (rc)
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return rc;
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afu->global_mmio_size = val;
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/*
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* Per-process MMIO
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*/
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rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
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if (rc)
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return rc;
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afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2);
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afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
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rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
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if (rc)
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return rc;
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afu->pp_mmio_offset += (u64) val << 32;
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rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
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if (rc)
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return rc;
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afu->pp_mmio_stride = val;
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return 0;
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}
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static int read_afu_control(struct pci_dev *dev, struct ocxl_afu_config *afu)
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{
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int pos;
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u8 val8;
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u16 val16;
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pos = find_dvsec_afu_ctrl(dev, afu->idx);
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if (!pos) {
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dev_err(&dev->dev, "Can't find AFU control DVSEC for AFU %d\n",
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afu->idx);
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return -ENODEV;
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}
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afu->dvsec_afu_control_pos = pos;
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pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_SUP, &val8);
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afu->pasid_supported_log = EXTRACT_BITS(val8, 0, 4);
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pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP, &val16);
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afu->actag_supported = EXTRACT_BITS(val16, 0, 11);
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return 0;
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}
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static bool char_allowed(int c)
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{
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/*
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* Permitted Characters : Alphanumeric, hyphen, underscore, comma
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*/
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if ((c >= 0x30 && c <= 0x39) /* digits */ ||
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(c >= 0x41 && c <= 0x5A) /* upper case */ ||
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(c >= 0x61 && c <= 0x7A) /* lower case */ ||
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c == 0 /* NULL */ ||
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c == 0x2D /* - */ ||
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c == 0x5F /* _ */ ||
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c == 0x2C /* , */)
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return true;
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return false;
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}
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static int validate_afu(struct pci_dev *dev, struct ocxl_afu_config *afu)
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{
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int i;
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if (!afu->name[0]) {
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dev_err(&dev->dev, "Empty AFU name\n");
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return -EINVAL;
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}
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for (i = 0; i < OCXL_TEMPL_NAME_LEN; i++) {
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if (!char_allowed(afu->name[i])) {
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dev_err(&dev->dev,
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"Invalid character in AFU name\n");
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return -EINVAL;
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}
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}
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if (afu->global_mmio_bar != 0 &&
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afu->global_mmio_bar != 2 &&
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afu->global_mmio_bar != 4) {
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dev_err(&dev->dev, "Invalid global MMIO bar number\n");
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return -EINVAL;
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}
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if (afu->pp_mmio_bar != 0 &&
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afu->pp_mmio_bar != 2 &&
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afu->pp_mmio_bar != 4) {
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dev_err(&dev->dev, "Invalid per-process MMIO bar number\n");
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return -EINVAL;
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}
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return 0;
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}
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int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn,
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struct ocxl_afu_config *afu, u8 afu_idx)
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{
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int rc;
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u32 val32;
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/*
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* First, we need to write the AFU idx for the AFU we want to
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* access.
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*/
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WARN_ON((afu_idx & OCXL_DVSEC_AFU_IDX_MASK) != afu_idx);
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afu->idx = afu_idx;
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pci_write_config_byte(dev,
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fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
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afu->idx);
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rc = read_afu_name(dev, fn, afu);
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if (rc)
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return rc;
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rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_AFU_VERSION, &val32);
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if (rc)
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return rc;
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afu->version_major = EXTRACT_BITS(val32, 24, 31);
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afu->version_minor = EXTRACT_BITS(val32, 16, 23);
|
|
afu->afuc_type = EXTRACT_BITS(val32, 14, 15);
|
|
afu->afum_type = EXTRACT_BITS(val32, 12, 13);
|
|
afu->profile = EXTRACT_BITS(val32, 0, 7);
|
|
|
|
rc = read_afu_mmio(dev, fn, afu);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MEM_SZ, &val32);
|
|
if (rc)
|
|
return rc;
|
|
afu->log_mem_size = EXTRACT_BITS(val32, 0, 7);
|
|
|
|
rc = read_afu_control(dev, afu);
|
|
if (rc)
|
|
return rc;
|
|
|
|
dev_dbg(&dev->dev, "AFU configuration:\n");
|
|
dev_dbg(&dev->dev, " name = %s\n", afu->name);
|
|
dev_dbg(&dev->dev, " version = %d.%d\n", afu->version_major,
|
|
afu->version_minor);
|
|
dev_dbg(&dev->dev, " global mmio bar = %hhu\n", afu->global_mmio_bar);
|
|
dev_dbg(&dev->dev, " global mmio offset = %#llx\n",
|
|
afu->global_mmio_offset);
|
|
dev_dbg(&dev->dev, " global mmio size = %#x\n", afu->global_mmio_size);
|
|
dev_dbg(&dev->dev, " pp mmio bar = %hhu\n", afu->pp_mmio_bar);
|
|
dev_dbg(&dev->dev, " pp mmio offset = %#llx\n", afu->pp_mmio_offset);
|
|
dev_dbg(&dev->dev, " pp mmio stride = %#x\n", afu->pp_mmio_stride);
|
|
dev_dbg(&dev->dev, " mem size (log) = %hhu\n", afu->log_mem_size);
|
|
dev_dbg(&dev->dev, " pasid supported (log) = %u\n",
|
|
afu->pasid_supported_log);
|
|
dev_dbg(&dev->dev, " actag supported = %u\n",
|
|
afu->actag_supported);
|
|
|
|
rc = validate_afu(dev, afu);
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ocxl_config_read_afu);
|
|
|
|
int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
|
|
u16 *supported)
|
|
{
|
|
int rc;
|
|
|
|
/*
|
|
* This is really a simple wrapper for the kernel API, to
|
|
* avoid an external driver using ocxl as a library to call
|
|
* platform-dependent code
|
|
*/
|
|
rc = pnv_ocxl_get_actag(dev, base, enabled, supported);
|
|
if (rc) {
|
|
dev_err(&dev->dev, "Can't get actag for device: %d\n", rc);
|
|
return rc;
|
|
}
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ocxl_config_get_actag_info);
|
|
|
|
void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
|
|
int actag_count)
|
|
{
|
|
u16 val;
|
|
|
|
val = actag_count & OCXL_DVSEC_ACTAG_MASK;
|
|
pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
|
|
|
|
val = actag_base & OCXL_DVSEC_ACTAG_MASK;
|
|
pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ocxl_config_set_afu_actag);
|
|
|
|
int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count)
|
|
{
|
|
return pnv_ocxl_get_pasid_count(dev, count);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ocxl_config_get_pasid_info);
|
|
|
|
void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
|
|
u32 pasid_count_log)
|
|
{
|
|
u8 val8;
|
|
u32 val32;
|
|
|
|
val8 = pasid_count_log & OCXL_DVSEC_PASID_LOG_MASK;
|
|
pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_EN, val8);
|
|
|
|
pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
|
|
&val32);
|
|
val32 &= ~OCXL_DVSEC_PASID_MASK;
|
|
val32 |= pasid_base & OCXL_DVSEC_PASID_MASK;
|
|
pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
|
|
val32);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ocxl_config_set_afu_pasid);
|
|
|
|
void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
|
|
{
|
|
u8 val;
|
|
|
|
pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
|
|
if (enable)
|
|
val |= 1;
|
|
else
|
|
val &= 0xFE;
|
|
pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ocxl_config_set_afu_state);
|
|
|
|
int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
|
|
{
|
|
u32 val;
|
|
__be32 *be32ptr;
|
|
u8 timers;
|
|
int i, rc;
|
|
long recv_cap;
|
|
char *recv_rate;
|
|
|
|
/*
|
|
* Skip on function != 0, as the TL can only be defined on 0
|
|
*/
|
|
if (PCI_FUNC(dev->devfn) != 0)
|
|
return 0;
|
|
|
|
recv_rate = kzalloc(PNV_OCXL_TL_RATE_BUF_SIZE, GFP_KERNEL);
|
|
if (!recv_rate)
|
|
return -ENOMEM;
|
|
/*
|
|
* The spec defines 64 templates for messages in the
|
|
* Transaction Layer (TL).
|
|
*
|
|
* The host and device each support a subset, so we need to
|
|
* configure the transmitters on each side to send only
|
|
* templates the receiver understands, at a rate the receiver
|
|
* can process. Per the spec, template 0 must be supported by
|
|
* everybody. That's the template which has been used by the
|
|
* host and device so far.
|
|
*
|
|
* The sending rate limit must be set before the template is
|
|
* enabled.
|
|
*/
|
|
|
|
/*
|
|
* Device -> host
|
|
*/
|
|
rc = pnv_ocxl_get_tl_cap(dev, &recv_cap, recv_rate,
|
|
PNV_OCXL_TL_RATE_BUF_SIZE);
|
|
if (rc)
|
|
goto out;
|
|
|
|
for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
|
|
be32ptr = (__be32 *) &recv_rate[i];
|
|
pci_write_config_dword(dev,
|
|
tl_dvsec + OCXL_DVSEC_TL_SEND_RATE + i,
|
|
be32_to_cpu(*be32ptr));
|
|
}
|
|
val = recv_cap >> 32;
|
|
pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
|
|
val = recv_cap & GENMASK(31, 0);
|
|
pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
|
|
|
|
/*
|
|
* Host -> device
|
|
*/
|
|
for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
|
|
pci_read_config_dword(dev,
|
|
tl_dvsec + OCXL_DVSEC_TL_RECV_RATE + i,
|
|
&val);
|
|
be32ptr = (__be32 *) &recv_rate[i];
|
|
*be32ptr = cpu_to_be32(val);
|
|
}
|
|
pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
|
|
recv_cap = (long) val << 32;
|
|
pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
|
|
recv_cap |= val;
|
|
|
|
rc = pnv_ocxl_set_tl_conf(dev, recv_cap, __pa(recv_rate),
|
|
PNV_OCXL_TL_RATE_BUF_SIZE);
|
|
if (rc)
|
|
goto out;
|
|
|
|
/*
|
|
* Opencapi commands needing to be retried are classified per
|
|
* the TL in 2 groups: short and long commands.
|
|
*
|
|
* The short back off timer it not used for now. It will be
|
|
* for opencapi 4.0.
|
|
*
|
|
* The long back off timer is typically used when an AFU hits
|
|
* a page fault but the NPU is already processing one. So the
|
|
* AFU needs to wait before it can resubmit. Having a value
|
|
* too low doesn't break anything, but can generate extra
|
|
* traffic on the link.
|
|
* We set it to 1.6 us for now. It's shorter than, but in the
|
|
* same order of magnitude as the time spent to process a page
|
|
* fault.
|
|
*/
|
|
timers = 0x2 << 4; /* long timer = 1.6 us */
|
|
pci_write_config_byte(dev, tl_dvsec + OCXL_DVSEC_TL_BACKOFF_TIMERS,
|
|
timers);
|
|
|
|
rc = 0;
|
|
out:
|
|
kfree(recv_rate);
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ocxl_config_set_TL);
|
|
|
|
int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
|
|
{
|
|
u32 val;
|
|
unsigned long timeout;
|
|
|
|
pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
|
|
&val);
|
|
if (EXTRACT_BIT(val, 20)) {
|
|
dev_err(&dev->dev,
|
|
"Can't terminate PASID %#x, previous termination didn't complete\n",
|
|
pasid);
|
|
return -EBUSY;
|
|
}
|
|
|
|
val &= ~OCXL_DVSEC_PASID_MASK;
|
|
val |= pasid & OCXL_DVSEC_PASID_MASK;
|
|
val |= BIT(20);
|
|
pci_write_config_dword(dev,
|
|
afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
|
|
val);
|
|
|
|
timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
|
|
pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
|
|
&val);
|
|
while (EXTRACT_BIT(val, 20)) {
|
|
if (time_after_eq(jiffies, timeout)) {
|
|
dev_err(&dev->dev,
|
|
"Timeout while waiting for AFU to terminate PASID %#x\n",
|
|
pasid);
|
|
return -EBUSY;
|
|
}
|
|
cpu_relax();
|
|
pci_read_config_dword(dev,
|
|
afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
|
|
&val);
|
|
}
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ocxl_config_terminate_pasid);
|
|
|
|
void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
|
|
u32 tag_count)
|
|
{
|
|
u32 val;
|
|
|
|
val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16;
|
|
val |= tag_count & OCXL_DVSEC_ACTAG_MASK;
|
|
pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG,
|
|
val);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ocxl_config_set_actag);
|