![Jie Yang](/assets/img/avatar_default.png)
INT3438 is the ADSP device on Wildcat Point platform with 2 DW DMA engines built In. The DMA engines are used for DSP FW loading and audio data transferring. These DMA engine probing need the clock, without it, probing may failed and can't go forward. Add LPSS device "INT3438" for Wildcat Point PCH, to provide clock for its ADSP DMA engine probing. Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
749 lines
18 KiB
C
749 lines
18 KiB
C
/*
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* ACPI support for Intel Lynxpoint LPSS.
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*
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* Copyright (C) 2013, Intel Corporation
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* Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
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* Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/clk-lpss.h>
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#include <linux/pm_runtime.h>
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#include <linux/delay.h>
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#include "internal.h"
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ACPI_MODULE_NAME("acpi_lpss");
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#ifdef CONFIG_X86_INTEL_LPSS
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#define LPSS_ADDR(desc) ((unsigned long)&desc)
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#define LPSS_CLK_SIZE 0x04
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#define LPSS_LTR_SIZE 0x18
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/* Offsets relative to LPSS_PRIVATE_OFFSET */
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#define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
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#define LPSS_RESETS 0x04
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#define LPSS_RESETS_RESET_FUNC BIT(0)
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#define LPSS_RESETS_RESET_APB BIT(1)
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#define LPSS_GENERAL 0x08
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#define LPSS_GENERAL_LTR_MODE_SW BIT(2)
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#define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
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#define LPSS_SW_LTR 0x10
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#define LPSS_AUTO_LTR 0x14
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#define LPSS_LTR_SNOOP_REQ BIT(15)
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#define LPSS_LTR_SNOOP_MASK 0x0000FFFF
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#define LPSS_LTR_SNOOP_LAT_1US 0x800
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#define LPSS_LTR_SNOOP_LAT_32US 0xC00
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#define LPSS_LTR_SNOOP_LAT_SHIFT 5
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#define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
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#define LPSS_LTR_MAX_VAL 0x3FF
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#define LPSS_TX_INT 0x20
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#define LPSS_TX_INT_MASK BIT(1)
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#define LPSS_PRV_REG_COUNT 9
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struct lpss_shared_clock {
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const char *name;
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unsigned long rate;
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struct clk *clk;
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};
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struct lpss_private_data;
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struct lpss_device_desc {
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bool clk_required;
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const char *clkdev_name;
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bool ltr_required;
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unsigned int prv_offset;
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size_t prv_size_override;
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bool clk_divider;
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bool clk_gate;
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bool save_ctx;
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struct lpss_shared_clock *shared_clock;
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void (*setup)(struct lpss_private_data *pdata);
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};
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static struct lpss_device_desc lpss_dma_desc = {
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.clk_required = true,
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.clkdev_name = "hclk",
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};
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struct lpss_private_data {
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void __iomem *mmio_base;
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resource_size_t mmio_size;
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struct clk *clk;
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const struct lpss_device_desc *dev_desc;
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u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
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};
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static void lpss_uart_setup(struct lpss_private_data *pdata)
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{
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unsigned int offset;
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u32 reg;
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offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
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reg = readl(pdata->mmio_base + offset);
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writel(reg | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
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offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
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reg = readl(pdata->mmio_base + offset);
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writel(reg | LPSS_GENERAL_UART_RTS_OVRD, pdata->mmio_base + offset);
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}
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static void lpss_i2c_setup(struct lpss_private_data *pdata)
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{
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unsigned int offset;
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u32 val;
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offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
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val = readl(pdata->mmio_base + offset);
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val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
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writel(val, pdata->mmio_base + offset);
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}
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static struct lpss_device_desc wpt_dev_desc = {
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.clk_required = true,
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.prv_offset = 0x800,
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.ltr_required = true,
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.clk_divider = true,
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.clk_gate = true,
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};
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static struct lpss_device_desc lpt_dev_desc = {
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.clk_required = true,
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.prv_offset = 0x800,
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.ltr_required = true,
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.clk_divider = true,
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.clk_gate = true,
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};
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static struct lpss_device_desc lpt_i2c_dev_desc = {
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.clk_required = true,
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.prv_offset = 0x800,
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.ltr_required = true,
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.clk_gate = true,
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};
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static struct lpss_device_desc lpt_uart_dev_desc = {
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.clk_required = true,
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.prv_offset = 0x800,
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.ltr_required = true,
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.clk_divider = true,
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.clk_gate = true,
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.setup = lpss_uart_setup,
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};
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static struct lpss_device_desc lpt_sdio_dev_desc = {
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.prv_offset = 0x1000,
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.prv_size_override = 0x1018,
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.ltr_required = true,
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};
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static struct lpss_shared_clock pwm_clock = {
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.name = "pwm_clk",
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.rate = 25000000,
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};
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static struct lpss_device_desc byt_pwm_dev_desc = {
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.clk_required = true,
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.save_ctx = true,
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.shared_clock = &pwm_clock,
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};
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static struct lpss_device_desc byt_uart_dev_desc = {
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.clk_required = true,
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.prv_offset = 0x800,
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.clk_divider = true,
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.clk_gate = true,
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.save_ctx = true,
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.setup = lpss_uart_setup,
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};
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static struct lpss_device_desc byt_spi_dev_desc = {
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.clk_required = true,
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.prv_offset = 0x400,
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.clk_divider = true,
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.clk_gate = true,
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.save_ctx = true,
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};
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static struct lpss_device_desc byt_sdio_dev_desc = {
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.clk_required = true,
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};
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static struct lpss_shared_clock i2c_clock = {
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.name = "i2c_clk",
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.rate = 100000000,
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};
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static struct lpss_device_desc byt_i2c_dev_desc = {
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.clk_required = true,
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.prv_offset = 0x800,
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.save_ctx = true,
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.shared_clock = &i2c_clock,
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.setup = lpss_i2c_setup,
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};
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#else
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#define LPSS_ADDR(desc) (0UL)
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#endif /* CONFIG_X86_INTEL_LPSS */
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static const struct acpi_device_id acpi_lpss_device_ids[] = {
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/* Generic LPSS devices */
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{ "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
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/* Lynxpoint LPSS devices */
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{ "INT33C0", LPSS_ADDR(lpt_dev_desc) },
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{ "INT33C1", LPSS_ADDR(lpt_dev_desc) },
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{ "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
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{ "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
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{ "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
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{ "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
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{ "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
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{ "INT33C7", },
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/* BayTrail LPSS devices */
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{ "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
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{ "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
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{ "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
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{ "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
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{ "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
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{ "INT33B2", },
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{ "INT33FC", },
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{ "INT3430", LPSS_ADDR(lpt_dev_desc) },
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{ "INT3431", LPSS_ADDR(lpt_dev_desc) },
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{ "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
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{ "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
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{ "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
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{ "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
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{ "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
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{ "INT3437", },
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{ "INT3438", LPSS_ADDR(wpt_dev_desc) },
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{ }
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};
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#ifdef CONFIG_X86_INTEL_LPSS
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static int is_memory(struct acpi_resource *res, void *not_used)
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{
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struct resource r;
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return !acpi_dev_resource_memory(res, &r);
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}
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/* LPSS main clock device. */
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static struct platform_device *lpss_clk_dev;
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static inline void lpt_register_clock_device(void)
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{
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lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
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}
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static int register_device_clock(struct acpi_device *adev,
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struct lpss_private_data *pdata)
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{
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const struct lpss_device_desc *dev_desc = pdata->dev_desc;
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struct lpss_shared_clock *shared_clock = dev_desc->shared_clock;
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const char *devname = dev_name(&adev->dev);
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struct clk *clk = ERR_PTR(-ENODEV);
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struct lpss_clk_data *clk_data;
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const char *parent, *clk_name;
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void __iomem *prv_base;
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if (!lpss_clk_dev)
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lpt_register_clock_device();
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clk_data = platform_get_drvdata(lpss_clk_dev);
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if (!clk_data)
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return -ENODEV;
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if (dev_desc->clkdev_name) {
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clk_register_clkdev(clk_data->clk, dev_desc->clkdev_name,
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devname);
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return 0;
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}
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if (!pdata->mmio_base
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|| pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
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return -ENODATA;
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parent = clk_data->name;
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prv_base = pdata->mmio_base + dev_desc->prv_offset;
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if (shared_clock) {
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clk = shared_clock->clk;
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if (!clk) {
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clk = clk_register_fixed_rate(NULL, shared_clock->name,
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"lpss_clk", 0,
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shared_clock->rate);
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shared_clock->clk = clk;
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}
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parent = shared_clock->name;
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}
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if (dev_desc->clk_gate) {
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clk = clk_register_gate(NULL, devname, parent, 0,
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prv_base, 0, 0, NULL);
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parent = devname;
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}
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if (dev_desc->clk_divider) {
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/* Prevent division by zero */
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if (!readl(prv_base))
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writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
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clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
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if (!clk_name)
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return -ENOMEM;
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clk = clk_register_fractional_divider(NULL, clk_name, parent,
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0, prv_base,
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1, 15, 16, 15, 0, NULL);
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parent = clk_name;
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clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
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if (!clk_name) {
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kfree(parent);
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return -ENOMEM;
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}
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clk = clk_register_gate(NULL, clk_name, parent,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
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prv_base, 31, 0, NULL);
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kfree(parent);
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kfree(clk_name);
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}
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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pdata->clk = clk;
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clk_register_clkdev(clk, NULL, devname);
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return 0;
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}
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static int acpi_lpss_create_device(struct acpi_device *adev,
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const struct acpi_device_id *id)
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{
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struct lpss_device_desc *dev_desc;
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struct lpss_private_data *pdata;
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struct resource_list_entry *rentry;
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struct list_head resource_list;
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struct platform_device *pdev;
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int ret;
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dev_desc = (struct lpss_device_desc *)id->driver_data;
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if (!dev_desc) {
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pdev = acpi_create_platform_device(adev);
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return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
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}
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pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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INIT_LIST_HEAD(&resource_list);
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ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
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if (ret < 0)
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goto err_out;
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list_for_each_entry(rentry, &resource_list, node)
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if (resource_type(&rentry->res) == IORESOURCE_MEM) {
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if (dev_desc->prv_size_override)
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pdata->mmio_size = dev_desc->prv_size_override;
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else
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pdata->mmio_size = resource_size(&rentry->res);
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pdata->mmio_base = ioremap(rentry->res.start,
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pdata->mmio_size);
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break;
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}
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acpi_dev_free_resource_list(&resource_list);
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pdata->dev_desc = dev_desc;
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if (dev_desc->clk_required) {
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ret = register_device_clock(adev, pdata);
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if (ret) {
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/* Skip the device, but continue the namespace scan. */
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ret = 0;
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goto err_out;
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}
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}
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/*
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* This works around a known issue in ACPI tables where LPSS devices
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* have _PS0 and _PS3 without _PSC (and no power resources), so
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* acpi_bus_init_power() will assume that the BIOS has put them into D0.
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*/
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ret = acpi_device_fix_up_power(adev);
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if (ret) {
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/* Skip the device, but continue the namespace scan. */
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ret = 0;
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goto err_out;
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}
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if (dev_desc->setup)
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dev_desc->setup(pdata);
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adev->driver_data = pdata;
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pdev = acpi_create_platform_device(adev);
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if (!IS_ERR_OR_NULL(pdev)) {
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device_enable_async_suspend(&pdev->dev);
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return 1;
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}
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ret = PTR_ERR(pdev);
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adev->driver_data = NULL;
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err_out:
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kfree(pdata);
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return ret;
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}
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static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
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{
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return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
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}
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static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
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unsigned int reg)
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{
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writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
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}
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static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
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{
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struct acpi_device *adev;
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struct lpss_private_data *pdata;
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unsigned long flags;
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int ret;
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ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
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if (WARN_ON(ret))
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return ret;
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spin_lock_irqsave(&dev->power.lock, flags);
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if (pm_runtime_suspended(dev)) {
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ret = -EAGAIN;
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goto out;
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}
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pdata = acpi_driver_data(adev);
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if (WARN_ON(!pdata || !pdata->mmio_base)) {
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ret = -ENODEV;
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goto out;
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}
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*val = __lpss_reg_read(pdata, reg);
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out:
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spin_unlock_irqrestore(&dev->power.lock, flags);
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return ret;
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}
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static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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u32 ltr_value = 0;
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unsigned int reg;
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int ret;
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reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
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ret = lpss_reg_read(dev, reg, <r_value);
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if (ret)
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return ret;
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return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
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}
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static ssize_t lpss_ltr_mode_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 ltr_mode = 0;
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char *outstr;
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int ret;
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ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode);
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if (ret)
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return ret;
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outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
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return sprintf(buf, "%s\n", outstr);
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}
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|
|
static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
|
|
static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
|
|
static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
|
|
|
|
static struct attribute *lpss_attrs[] = {
|
|
&dev_attr_auto_ltr.attr,
|
|
&dev_attr_sw_ltr.attr,
|
|
&dev_attr_ltr_mode.attr,
|
|
NULL,
|
|
};
|
|
|
|
static struct attribute_group lpss_attr_group = {
|
|
.attrs = lpss_attrs,
|
|
.name = "lpss_ltr",
|
|
};
|
|
|
|
static void acpi_lpss_set_ltr(struct device *dev, s32 val)
|
|
{
|
|
struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
|
|
u32 ltr_mode, ltr_val;
|
|
|
|
ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
|
|
if (val < 0) {
|
|
if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
|
|
ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
|
|
__lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
|
|
}
|
|
return;
|
|
}
|
|
ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
|
|
if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
|
|
ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
|
|
val = LPSS_LTR_MAX_VAL;
|
|
} else if (val > LPSS_LTR_MAX_VAL) {
|
|
ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
|
|
val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
|
|
} else {
|
|
ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
|
|
}
|
|
ltr_val |= val;
|
|
__lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
|
|
if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
|
|
ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
|
|
__lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
/**
|
|
* acpi_lpss_save_ctx() - Save the private registers of LPSS device
|
|
* @dev: LPSS device
|
|
*
|
|
* Most LPSS devices have private registers which may loose their context when
|
|
* the device is powered down. acpi_lpss_save_ctx() saves those registers into
|
|
* prv_reg_ctx array.
|
|
*/
|
|
static void acpi_lpss_save_ctx(struct device *dev)
|
|
{
|
|
struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
|
|
unsigned long offset = i * sizeof(u32);
|
|
|
|
pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
|
|
dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
|
|
pdata->prv_reg_ctx[i], offset);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
|
|
* @dev: LPSS device
|
|
*
|
|
* Restores the registers that were previously stored with acpi_lpss_save_ctx().
|
|
*/
|
|
static void acpi_lpss_restore_ctx(struct device *dev)
|
|
{
|
|
struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
|
|
unsigned int i;
|
|
|
|
/*
|
|
* The following delay is needed or the subsequent write operations may
|
|
* fail. The LPSS devices are actually PCI devices and the PCI spec
|
|
* expects 10ms delay before the device can be accessed after D3 to D0
|
|
* transition.
|
|
*/
|
|
msleep(10);
|
|
|
|
for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
|
|
unsigned long offset = i * sizeof(u32);
|
|
|
|
__lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
|
|
dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
|
|
pdata->prv_reg_ctx[i], offset);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int acpi_lpss_suspend_late(struct device *dev)
|
|
{
|
|
int ret = pm_generic_suspend_late(dev);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
acpi_lpss_save_ctx(dev);
|
|
return acpi_dev_suspend_late(dev);
|
|
}
|
|
|
|
static int acpi_lpss_restore_early(struct device *dev)
|
|
{
|
|
int ret = acpi_dev_resume_early(dev);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
acpi_lpss_restore_ctx(dev);
|
|
return pm_generic_resume_early(dev);
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
static int acpi_lpss_runtime_suspend(struct device *dev)
|
|
{
|
|
int ret = pm_generic_runtime_suspend(dev);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
acpi_lpss_save_ctx(dev);
|
|
return acpi_dev_runtime_suspend(dev);
|
|
}
|
|
|
|
static int acpi_lpss_runtime_resume(struct device *dev)
|
|
{
|
|
int ret = acpi_dev_runtime_resume(dev);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
acpi_lpss_restore_ctx(dev);
|
|
return pm_generic_runtime_resume(dev);
|
|
}
|
|
#endif /* CONFIG_PM_RUNTIME */
|
|
#endif /* CONFIG_PM */
|
|
|
|
static struct dev_pm_domain acpi_lpss_pm_domain = {
|
|
.ops = {
|
|
#ifdef CONFIG_PM_SLEEP
|
|
.suspend_late = acpi_lpss_suspend_late,
|
|
.restore_early = acpi_lpss_restore_early,
|
|
.prepare = acpi_subsys_prepare,
|
|
.complete = acpi_subsys_complete,
|
|
.suspend = acpi_subsys_suspend,
|
|
.resume_early = acpi_subsys_resume_early,
|
|
.freeze = acpi_subsys_freeze,
|
|
.poweroff = acpi_subsys_suspend,
|
|
.poweroff_late = acpi_subsys_suspend_late,
|
|
#endif
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
.runtime_suspend = acpi_lpss_runtime_suspend,
|
|
.runtime_resume = acpi_lpss_runtime_resume,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
static int acpi_lpss_platform_notify(struct notifier_block *nb,
|
|
unsigned long action, void *data)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(data);
|
|
struct lpss_private_data *pdata;
|
|
struct acpi_device *adev;
|
|
const struct acpi_device_id *id;
|
|
|
|
id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
|
|
if (!id || !id->driver_data)
|
|
return 0;
|
|
|
|
if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
|
|
return 0;
|
|
|
|
pdata = acpi_driver_data(adev);
|
|
if (!pdata || !pdata->mmio_base)
|
|
return 0;
|
|
|
|
if (pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
|
|
dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
|
|
return 0;
|
|
}
|
|
|
|
switch (action) {
|
|
case BUS_NOTIFY_BOUND_DRIVER:
|
|
if (pdata->dev_desc->save_ctx)
|
|
pdev->dev.pm_domain = &acpi_lpss_pm_domain;
|
|
break;
|
|
case BUS_NOTIFY_UNBOUND_DRIVER:
|
|
if (pdata->dev_desc->save_ctx)
|
|
pdev->dev.pm_domain = NULL;
|
|
break;
|
|
case BUS_NOTIFY_ADD_DEVICE:
|
|
if (pdata->dev_desc->ltr_required)
|
|
return sysfs_create_group(&pdev->dev.kobj,
|
|
&lpss_attr_group);
|
|
case BUS_NOTIFY_DEL_DEVICE:
|
|
if (pdata->dev_desc->ltr_required)
|
|
sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct notifier_block acpi_lpss_nb = {
|
|
.notifier_call = acpi_lpss_platform_notify,
|
|
};
|
|
|
|
static void acpi_lpss_bind(struct device *dev)
|
|
{
|
|
struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
|
|
|
|
if (!pdata || !pdata->mmio_base || !pdata->dev_desc->ltr_required)
|
|
return;
|
|
|
|
if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
|
|
dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
|
|
else
|
|
dev_err(dev, "MMIO size insufficient to access LTR\n");
|
|
}
|
|
|
|
static void acpi_lpss_unbind(struct device *dev)
|
|
{
|
|
dev->power.set_latency_tolerance = NULL;
|
|
}
|
|
|
|
static struct acpi_scan_handler lpss_handler = {
|
|
.ids = acpi_lpss_device_ids,
|
|
.attach = acpi_lpss_create_device,
|
|
.bind = acpi_lpss_bind,
|
|
.unbind = acpi_lpss_unbind,
|
|
};
|
|
|
|
void __init acpi_lpss_init(void)
|
|
{
|
|
if (!lpt_clk_init()) {
|
|
bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
|
|
acpi_scan_add_handler(&lpss_handler);
|
|
}
|
|
}
|
|
|
|
#else
|
|
|
|
static struct acpi_scan_handler lpss_handler = {
|
|
.ids = acpi_lpss_device_ids,
|
|
};
|
|
|
|
void __init acpi_lpss_init(void)
|
|
{
|
|
acpi_scan_add_handler(&lpss_handler);
|
|
}
|
|
|
|
#endif /* CONFIG_X86_INTEL_LPSS */
|