![John Crispin](/assets/img/avatar_default.png)
Support for the external interrupt unit was broken when the code was converted to devicetree support. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4231/
437 lines
10 KiB
C
437 lines
10 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/irqdomain.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/bootinfo.h>
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#include <asm/irq_cpu.h>
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#include <lantiq_soc.h>
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#include <irq.h>
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/* register definitions - internal irqs */
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#define LTQ_ICU_IM0_ISR 0x0000
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#define LTQ_ICU_IM0_IER 0x0008
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#define LTQ_ICU_IM0_IOSR 0x0010
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#define LTQ_ICU_IM0_IRSR 0x0018
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#define LTQ_ICU_IM0_IMR 0x0020
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#define LTQ_ICU_IM1_ISR 0x0028
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#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
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/* register definitions - external irqs */
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#define LTQ_EIU_EXIN_C 0x0000
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#define LTQ_EIU_EXIN_INIC 0x0004
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#define LTQ_EIU_EXIN_INEN 0x000C
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/* irq numbers used by the external interrupt unit (EIU) */
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#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
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#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
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#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
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#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
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#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
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#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
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#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
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#define XWAY_EXIN_COUNT 3
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#define MAX_EIU 6
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/* the performance counter */
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#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
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/*
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* irqs generated by devices attached to the EBU need to be acked in
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* a special manner
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*/
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#define LTQ_ICU_EBU_IRQ 22
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#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
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#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
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#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
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#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
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/* our 2 ipi interrupts for VSMP */
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#define MIPS_CPU_IPI_RESCHED_IRQ 0
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#define MIPS_CPU_IPI_CALL_IRQ 1
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/* we have a cascade of 8 irqs */
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#define MIPS_CPU_IRQ_CASCADE 8
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#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
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int gic_present;
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#endif
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static unsigned short ltq_eiu_irq[MAX_EIU] = {
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LTQ_EIU_IR0,
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LTQ_EIU_IR1,
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LTQ_EIU_IR2,
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LTQ_EIU_IR3,
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LTQ_EIU_IR4,
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LTQ_EIU_IR5,
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};
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static int exin_avail;
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static void __iomem *ltq_icu_membase[MAX_IM];
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static void __iomem *ltq_eiu_membase;
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static struct irq_domain *ltq_domain;
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void ltq_disable_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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int im = offset / INT_NUM_IM_OFFSET;
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offset %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
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}
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void ltq_mask_and_ack_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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u32 isr = LTQ_ICU_IM0_ISR;
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int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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int im = offset / INT_NUM_IM_OFFSET;
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offset %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
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ltq_icu_w32(im, BIT(offset), isr);
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}
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static void ltq_ack_irq(struct irq_data *d)
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{
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u32 isr = LTQ_ICU_IM0_ISR;
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int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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int im = offset / INT_NUM_IM_OFFSET;
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offset %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(im, BIT(offset), isr);
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}
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void ltq_enable_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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int im = offset / INT_NUM_IM_OFFSET;
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offset %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
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}
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static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
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{
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int i;
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ltq_enable_irq(d);
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for (i = 0; i < MAX_EIU; i++) {
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if (d->hwirq == ltq_eiu_irq[i]) {
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/* low level - we should really handle set_type */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
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(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
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/* clear all pending */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
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LTQ_EIU_EXIN_INIC);
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/* enable */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
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LTQ_EIU_EXIN_INEN);
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break;
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}
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}
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return 0;
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}
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static void ltq_shutdown_eiu_irq(struct irq_data *d)
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{
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int i;
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ltq_disable_irq(d);
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for (i = 0; i < MAX_EIU; i++) {
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if (d->hwirq == ltq_eiu_irq[i]) {
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/* disable */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
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LTQ_EIU_EXIN_INEN);
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break;
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}
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}
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}
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static struct irq_chip ltq_irq_type = {
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"icu",
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.irq_enable = ltq_enable_irq,
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.irq_disable = ltq_disable_irq,
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.irq_unmask = ltq_enable_irq,
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.irq_ack = ltq_ack_irq,
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.irq_mask = ltq_disable_irq,
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.irq_mask_ack = ltq_mask_and_ack_irq,
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};
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static struct irq_chip ltq_eiu_type = {
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"eiu",
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.irq_startup = ltq_startup_eiu_irq,
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.irq_shutdown = ltq_shutdown_eiu_irq,
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.irq_enable = ltq_enable_irq,
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.irq_disable = ltq_disable_irq,
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.irq_unmask = ltq_enable_irq,
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.irq_ack = ltq_ack_irq,
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.irq_mask = ltq_disable_irq,
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.irq_mask_ack = ltq_mask_and_ack_irq,
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};
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static void ltq_hw_irqdispatch(int module)
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{
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u32 irq;
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irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
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if (irq == 0)
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return;
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/*
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* silicon bug causes only the msb set to 1 to be valid. all
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* other bits might be bogus
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*/
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irq = __fls(irq);
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do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
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/* if this is a EBU irq, we need to ack it or get a deadlock */
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if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
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LTQ_EBU_PCC_ISTAT);
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}
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#define DEFINE_HWx_IRQDISPATCH(x) \
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static void ltq_hw ## x ## _irqdispatch(void) \
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{ \
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ltq_hw_irqdispatch(x); \
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}
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DEFINE_HWx_IRQDISPATCH(0)
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DEFINE_HWx_IRQDISPATCH(1)
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DEFINE_HWx_IRQDISPATCH(2)
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DEFINE_HWx_IRQDISPATCH(3)
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DEFINE_HWx_IRQDISPATCH(4)
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#if MIPS_CPU_TIMER_IRQ == 7
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static void ltq_hw5_irqdispatch(void)
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{
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do_IRQ(MIPS_CPU_TIMER_IRQ);
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}
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#else
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DEFINE_HWx_IRQDISPATCH(5)
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#endif
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#ifdef CONFIG_MIPS_MT_SMP
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void __init arch_init_ipiirq(int irq, struct irqaction *action)
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{
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setup_irq(irq, action);
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irq_set_handler(irq, handle_percpu_irq);
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}
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static void ltq_sw0_irqdispatch(void)
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{
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do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
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}
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static void ltq_sw1_irqdispatch(void)
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{
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do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
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}
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static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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{
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scheduler_ipi();
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return IRQ_HANDLED;
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}
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static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
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{
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smp_call_function_interrupt();
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return IRQ_HANDLED;
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}
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static struct irqaction irq_resched = {
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.handler = ipi_resched_interrupt,
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.flags = IRQF_PERCPU,
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.name = "IPI_resched"
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};
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static struct irqaction irq_call = {
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.handler = ipi_call_interrupt,
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.flags = IRQF_PERCPU,
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.name = "IPI_call"
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};
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#endif
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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unsigned int i;
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if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
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do_IRQ(MIPS_CPU_TIMER_IRQ);
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goto out;
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} else {
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for (i = 0; i < MAX_IM; i++) {
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if (pending & (CAUSEF_IP2 << i)) {
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ltq_hw_irqdispatch(i);
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goto out;
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}
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}
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}
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pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
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out:
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return;
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}
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static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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struct irq_chip *chip = <q_irq_type;
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int i;
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if (hw < MIPS_CPU_IRQ_CASCADE)
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return 0;
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for (i = 0; i < exin_avail; i++)
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if (hw == ltq_eiu_irq[i])
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chip = <q_eiu_type;
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irq_set_chip_and_handler(hw, chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops irq_domain_ops = {
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.xlate = irq_domain_xlate_onetwocell,
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.map = icu_map,
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};
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static struct irqaction cascade = {
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.handler = no_action,
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.name = "cascade",
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};
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int __init icu_of_init(struct device_node *node, struct device_node *parent)
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{
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struct device_node *eiu_node;
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struct resource res;
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int i;
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for (i = 0; i < MAX_IM; i++) {
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if (of_address_to_resource(node, i, &res))
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panic("Failed to get icu memory range");
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if (request_mem_region(res.start, resource_size(&res),
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res.name) < 0)
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pr_err("Failed to request icu memory");
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ltq_icu_membase[i] = ioremap_nocache(res.start,
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resource_size(&res));
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if (!ltq_icu_membase[i])
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panic("Failed to remap icu memory");
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}
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/* the external interrupts are optional and xway only */
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eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
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if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
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/* find out how many external irq sources we have */
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const __be32 *count = of_get_property(node,
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"lantiq,count", NULL);
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if (count)
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exin_avail = *count;
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if (exin_avail > MAX_EIU)
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exin_avail = MAX_EIU;
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if (request_mem_region(res.start, resource_size(&res),
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res.name) < 0)
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pr_err("Failed to request eiu memory");
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ltq_eiu_membase = ioremap_nocache(res.start,
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resource_size(&res));
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if (!ltq_eiu_membase)
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panic("Failed to remap eiu memory");
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}
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/* turn off all irqs by default */
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for (i = 0; i < MAX_IM; i++) {
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/* make sure all irqs are turned off by default */
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ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
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/* clear all possibly pending interrupts */
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ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
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}
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mips_cpu_irq_init();
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for (i = 0; i < MAX_IM; i++)
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setup_irq(i + 2, &cascade);
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if (cpu_has_vint) {
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pr_info("Setting up vectored interrupts\n");
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set_vi_handler(2, ltq_hw0_irqdispatch);
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set_vi_handler(3, ltq_hw1_irqdispatch);
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set_vi_handler(4, ltq_hw2_irqdispatch);
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set_vi_handler(5, ltq_hw3_irqdispatch);
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set_vi_handler(6, ltq_hw4_irqdispatch);
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set_vi_handler(7, ltq_hw5_irqdispatch);
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}
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ltq_domain = irq_domain_add_linear(node,
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(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
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&irq_domain_ops, 0);
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#if defined(CONFIG_MIPS_MT_SMP)
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if (cpu_has_vint) {
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pr_info("Setting up IPI vectored interrupts\n");
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set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
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set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
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}
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arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
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&irq_resched);
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arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
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#endif
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#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
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set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
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IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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#else
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set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
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IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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#endif
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/* tell oprofile which irq to use */
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cp0_perfcount_irq = LTQ_PERF_IRQ;
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/*
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* if the timer irq is not one of the mips irqs we need to
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* create a mapping
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*/
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if (MIPS_CPU_TIMER_IRQ != 7)
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irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
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return 0;
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}
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unsigned int __cpuinit get_c0_compare_int(void)
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{
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return MIPS_CPU_TIMER_IRQ;
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}
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static struct of_device_id __initdata of_irq_ids[] = {
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{ .compatible = "lantiq,icu", .data = icu_of_init },
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{},
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};
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void __init arch_init_irq(void)
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{
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of_irq_init(of_irq_ids);
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}
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