![Mark Rutland](/assets/img/avatar_default.png)
When initialising a PMU, there is a check to protect against races with other CPUs filling all of the available event slots. Since armpmu_add checks that an event can be scheduled, we do not need to do this at initialisation time. Furthermore the current code is broken because it assumes that atomic_inc_not_zero will unconditionally increment active_counts and then tries to decrement it again on failure. This patch removes the broken, redundant code. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Cc: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
774 lines
17 KiB
C
774 lines
17 KiB
C
#undef DEBUG
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/*
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* ARM performance counter support.
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*
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* Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
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* Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
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*
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* This code is based on the sparc64 perf event code, which is in turn based
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* on the x86 code. Callchain code is based on the ARM OProfile backtrace
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* code.
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*/
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#define pr_fmt(fmt) "hw perfevents: " fmt
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/uaccess.h>
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#include <asm/cputype.h>
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#include <asm/irq.h>
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#include <asm/irq_regs.h>
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#include <asm/pmu.h>
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#include <asm/stacktrace.h>
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static struct platform_device *pmu_device;
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/*
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* Hardware lock to serialize accesses to PMU registers. Needed for the
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* read/modify/write sequences.
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*/
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static DEFINE_RAW_SPINLOCK(pmu_lock);
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/*
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* ARMv6 supports a maximum of 3 events, starting from index 1. If we add
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* another platform that supports more, we need to increase this to be the
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* largest of all platforms.
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*
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* ARMv7 supports up to 32 events:
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* cycle counter CCNT + 31 events counters CNT0..30.
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* Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
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*/
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#define ARMPMU_MAX_HWEVENTS 33
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/* The events for a given CPU. */
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struct cpu_hw_events {
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/*
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* The events that are active on the CPU for the given index. Index 0
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* is reserved.
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*/
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struct perf_event *events[ARMPMU_MAX_HWEVENTS];
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/*
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* A 1 bit for an index indicates that the counter is being used for
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* an event. A 0 means that the counter can be used.
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*/
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unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
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/*
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* A 1 bit for an index indicates that the counter is actively being
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* used.
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*/
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unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
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};
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static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
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struct arm_pmu {
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enum arm_perf_pmu_ids id;
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const char *name;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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void (*enable)(struct hw_perf_event *evt, int idx);
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void (*disable)(struct hw_perf_event *evt, int idx);
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int (*get_event_idx)(struct cpu_hw_events *cpuc,
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struct hw_perf_event *hwc);
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u32 (*read_counter)(int idx);
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void (*write_counter)(int idx, u32 val);
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void (*start)(void);
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void (*stop)(void);
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void (*reset)(void *);
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const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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const unsigned (*event_map)[PERF_COUNT_HW_MAX];
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u32 raw_event_mask;
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int num_events;
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u64 max_period;
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};
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/* Set at runtime when we know what CPU type we are. */
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static const struct arm_pmu *armpmu;
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enum arm_perf_pmu_ids
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armpmu_get_pmu_id(void)
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{
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int id = -ENODEV;
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if (armpmu != NULL)
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id = armpmu->id;
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return id;
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}
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EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
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int
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armpmu_get_max_events(void)
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{
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int max_events = 0;
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if (armpmu != NULL)
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max_events = armpmu->num_events;
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return max_events;
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}
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EXPORT_SYMBOL_GPL(armpmu_get_max_events);
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int perf_num_counters(void)
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{
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return armpmu_get_max_events();
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}
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EXPORT_SYMBOL_GPL(perf_num_counters);
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#define HW_OP_UNSUPPORTED 0xFFFF
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#define C(_x) \
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PERF_COUNT_HW_CACHE_##_x
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#define CACHE_OP_UNSUPPORTED 0xFFFF
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static int
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armpmu_map_cache_event(u64 config)
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{
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unsigned int cache_type, cache_op, cache_result, ret;
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cache_type = (config >> 0) & 0xff;
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if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
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return -EINVAL;
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cache_op = (config >> 8) & 0xff;
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if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
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return -EINVAL;
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cache_result = (config >> 16) & 0xff;
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if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result];
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if (ret == CACHE_OP_UNSUPPORTED)
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return -ENOENT;
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return ret;
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}
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static int
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armpmu_map_event(u64 config)
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{
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int mapping = (*armpmu->event_map)[config];
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return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping;
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}
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static int
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armpmu_map_raw_event(u64 config)
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{
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return (int)(config & armpmu->raw_event_mask);
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}
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static int
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armpmu_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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{
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int ret = 0;
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if (unlikely(left <= -period)) {
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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if (unlikely(left <= 0)) {
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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if (left > (s64)armpmu->max_period)
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left = armpmu->max_period;
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local64_set(&hwc->prev_count, (u64)-left);
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armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
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perf_event_update_userpage(event);
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return ret;
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}
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static u64
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armpmu_event_update(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx, int overflow)
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{
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u64 delta, prev_raw_count, new_raw_count;
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again:
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = armpmu->read_counter(idx);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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goto again;
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new_raw_count &= armpmu->max_period;
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prev_raw_count &= armpmu->max_period;
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if (overflow)
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delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
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else
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delta = new_raw_count - prev_raw_count;
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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return new_raw_count;
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}
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static void
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armpmu_read(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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/* Don't read disabled counters! */
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if (hwc->idx < 0)
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return;
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armpmu_event_update(event, hwc, hwc->idx, 0);
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}
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static void
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armpmu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (!armpmu)
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return;
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/*
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* ARM pmu always has to update the counter, so ignore
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* PERF_EF_UPDATE, see comments in armpmu_start().
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*/
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if (!(hwc->state & PERF_HES_STOPPED)) {
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armpmu->disable(hwc, hwc->idx);
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barrier(); /* why? */
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armpmu_event_update(event, hwc, hwc->idx, 0);
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hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
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}
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}
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static void
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armpmu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (!armpmu)
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return;
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/*
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* ARM pmu always has to reprogram the period, so ignore
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* PERF_EF_RELOAD, see the comment below.
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*/
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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/*
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* Set the period again. Some counters can't be stopped, so when we
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* were stopped we simply disabled the IRQ source and the counter
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* may have been left counting. If we don't do this step then we may
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* get an interrupt too soon or *way* too late if the overflow has
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* happened since disabling.
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*/
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armpmu_event_set_period(event, hwc, hwc->idx);
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armpmu->enable(hwc, hwc->idx);
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}
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static void
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armpmu_del(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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WARN_ON(idx < 0);
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clear_bit(idx, cpuc->active_mask);
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armpmu_stop(event, PERF_EF_UPDATE);
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cpuc->events[idx] = NULL;
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clear_bit(idx, cpuc->used_mask);
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perf_event_update_userpage(event);
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}
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static int
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armpmu_add(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx;
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int err = 0;
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perf_pmu_disable(event->pmu);
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/* If we don't have a space for the counter then finish early. */
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idx = armpmu->get_event_idx(cpuc, hwc);
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if (idx < 0) {
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err = idx;
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goto out;
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}
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/*
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* If there is an event in the counter we are going to use then make
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* sure it is disabled.
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*/
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event->hw.idx = idx;
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armpmu->disable(hwc, idx);
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cpuc->events[idx] = event;
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set_bit(idx, cpuc->active_mask);
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hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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if (flags & PERF_EF_START)
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armpmu_start(event, PERF_EF_RELOAD);
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/* Propagate our changes to the userspace mapping. */
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perf_event_update_userpage(event);
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out:
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perf_pmu_enable(event->pmu);
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return err;
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}
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static struct pmu pmu;
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static int
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validate_event(struct cpu_hw_events *cpuc,
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struct perf_event *event)
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{
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struct hw_perf_event fake_event = event->hw;
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if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
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return 1;
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return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
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}
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static int
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validate_group(struct perf_event *event)
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{
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struct perf_event *sibling, *leader = event->group_leader;
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struct cpu_hw_events fake_pmu;
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memset(&fake_pmu, 0, sizeof(fake_pmu));
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if (!validate_event(&fake_pmu, leader))
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return -ENOSPC;
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list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
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if (!validate_event(&fake_pmu, sibling))
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return -ENOSPC;
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}
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if (!validate_event(&fake_pmu, event))
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return -ENOSPC;
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return 0;
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}
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static irqreturn_t armpmu_platform_irq(int irq, void *dev)
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{
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struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev);
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return plat->handle_irq(irq, dev, armpmu->handle_irq);
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}
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static int
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armpmu_reserve_hardware(void)
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{
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struct arm_pmu_platdata *plat;
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irq_handler_t handle_irq;
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int i, err = -ENODEV, irq;
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pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
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if (IS_ERR(pmu_device)) {
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pr_warning("unable to reserve pmu\n");
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return PTR_ERR(pmu_device);
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}
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init_pmu(ARM_PMU_DEVICE_CPU);
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plat = dev_get_platdata(&pmu_device->dev);
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if (plat && plat->handle_irq)
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handle_irq = armpmu_platform_irq;
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else
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handle_irq = armpmu->handle_irq;
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if (pmu_device->num_resources < 1) {
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pr_err("no irqs for PMUs defined\n");
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return -ENODEV;
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}
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for (i = 0; i < pmu_device->num_resources; ++i) {
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irq = platform_get_irq(pmu_device, i);
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if (irq < 0)
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continue;
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err = request_irq(irq, handle_irq,
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IRQF_DISABLED | IRQF_NOBALANCING,
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"armpmu", NULL);
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if (err) {
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pr_warning("unable to request IRQ%d for ARM perf "
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"counters\n", irq);
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break;
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}
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}
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if (err) {
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for (i = i - 1; i >= 0; --i) {
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irq = platform_get_irq(pmu_device, i);
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if (irq >= 0)
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free_irq(irq, NULL);
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}
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release_pmu(pmu_device);
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pmu_device = NULL;
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}
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return err;
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}
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static void
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armpmu_release_hardware(void)
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{
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int i, irq;
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for (i = pmu_device->num_resources - 1; i >= 0; --i) {
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irq = platform_get_irq(pmu_device, i);
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if (irq >= 0)
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free_irq(irq, NULL);
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}
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armpmu->stop();
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release_pmu(pmu_device);
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pmu_device = NULL;
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}
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static atomic_t active_events = ATOMIC_INIT(0);
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static DEFINE_MUTEX(pmu_reserve_mutex);
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static void
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hw_perf_event_destroy(struct perf_event *event)
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{
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if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
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armpmu_release_hardware();
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mutex_unlock(&pmu_reserve_mutex);
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}
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}
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static int
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__hw_perf_event_init(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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int mapping, err;
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/* Decode the generic type into an ARM event identifier. */
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if (PERF_TYPE_HARDWARE == event->attr.type) {
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mapping = armpmu_map_event(event->attr.config);
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} else if (PERF_TYPE_HW_CACHE == event->attr.type) {
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mapping = armpmu_map_cache_event(event->attr.config);
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} else if (PERF_TYPE_RAW == event->attr.type) {
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mapping = armpmu_map_raw_event(event->attr.config);
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} else {
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pr_debug("event type %x not supported\n", event->attr.type);
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return -EOPNOTSUPP;
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}
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if (mapping < 0) {
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pr_debug("event %x:%llx not supported\n", event->attr.type,
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event->attr.config);
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return mapping;
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}
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/*
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* Check whether we need to exclude the counter from certain modes.
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* The ARM performance counters are on all of the time so if someone
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* has asked us for some excludes then we have to fail.
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*/
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if (event->attr.exclude_kernel || event->attr.exclude_user ||
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event->attr.exclude_hv || event->attr.exclude_idle) {
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pr_debug("ARM performance counters do not support "
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"mode exclusion\n");
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return -EPERM;
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}
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/*
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* We don't assign an index until we actually place the event onto
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* hardware. Use -1 to signify that we haven't decided where to put it
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* yet. For SMP systems, each core has it's own PMU so we can't do any
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* clever allocation or constraints checking at this point.
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*/
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hwc->idx = -1;
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/*
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* Store the event encoding into the config_base field. config and
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* event_base are unused as the only 2 things we need to know are
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* the event mapping and the counter to use. The counter to use is
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* also the indx and the config_base is the event type.
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|
*/
|
|
hwc->config_base = (unsigned long)mapping;
|
|
hwc->config = 0;
|
|
hwc->event_base = 0;
|
|
|
|
if (!hwc->sample_period) {
|
|
hwc->sample_period = armpmu->max_period;
|
|
hwc->last_period = hwc->sample_period;
|
|
local64_set(&hwc->period_left, hwc->sample_period);
|
|
}
|
|
|
|
err = 0;
|
|
if (event->group_leader != event) {
|
|
err = validate_group(event);
|
|
if (err)
|
|
return -EINVAL;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int armpmu_event_init(struct perf_event *event)
|
|
{
|
|
int err = 0;
|
|
|
|
switch (event->attr.type) {
|
|
case PERF_TYPE_RAW:
|
|
case PERF_TYPE_HARDWARE:
|
|
case PERF_TYPE_HW_CACHE:
|
|
break;
|
|
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
if (!armpmu)
|
|
return -ENODEV;
|
|
|
|
event->destroy = hw_perf_event_destroy;
|
|
|
|
if (!atomic_inc_not_zero(&active_events)) {
|
|
mutex_lock(&pmu_reserve_mutex);
|
|
if (atomic_read(&active_events) == 0) {
|
|
err = armpmu_reserve_hardware();
|
|
}
|
|
|
|
if (!err)
|
|
atomic_inc(&active_events);
|
|
mutex_unlock(&pmu_reserve_mutex);
|
|
}
|
|
|
|
if (err)
|
|
return err;
|
|
|
|
err = __hw_perf_event_init(event);
|
|
if (err)
|
|
hw_perf_event_destroy(event);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void armpmu_enable(struct pmu *pmu)
|
|
{
|
|
/* Enable all of the perf events on hardware. */
|
|
int idx;
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
|
|
if (!armpmu)
|
|
return;
|
|
|
|
for (idx = 0; idx <= armpmu->num_events; ++idx) {
|
|
struct perf_event *event = cpuc->events[idx];
|
|
|
|
if (!event)
|
|
continue;
|
|
|
|
armpmu->enable(&event->hw, idx);
|
|
}
|
|
|
|
armpmu->start();
|
|
}
|
|
|
|
static void armpmu_disable(struct pmu *pmu)
|
|
{
|
|
if (armpmu)
|
|
armpmu->stop();
|
|
}
|
|
|
|
static struct pmu pmu = {
|
|
.pmu_enable = armpmu_enable,
|
|
.pmu_disable = armpmu_disable,
|
|
.event_init = armpmu_event_init,
|
|
.add = armpmu_add,
|
|
.del = armpmu_del,
|
|
.start = armpmu_start,
|
|
.stop = armpmu_stop,
|
|
.read = armpmu_read,
|
|
};
|
|
|
|
/* Include the PMU-specific implementations. */
|
|
#include "perf_event_xscale.c"
|
|
#include "perf_event_v6.c"
|
|
#include "perf_event_v7.c"
|
|
|
|
/*
|
|
* Ensure the PMU has sane values out of reset.
|
|
* This requires SMP to be available, so exists as a separate initcall.
|
|
*/
|
|
static int __init
|
|
armpmu_reset(void)
|
|
{
|
|
if (armpmu && armpmu->reset)
|
|
return on_each_cpu(armpmu->reset, NULL, 1);
|
|
return 0;
|
|
}
|
|
arch_initcall(armpmu_reset);
|
|
|
|
static int __init
|
|
init_hw_perf_events(void)
|
|
{
|
|
unsigned long cpuid = read_cpuid_id();
|
|
unsigned long implementor = (cpuid & 0xFF000000) >> 24;
|
|
unsigned long part_number = (cpuid & 0xFFF0);
|
|
|
|
/* ARM Ltd CPUs. */
|
|
if (0x41 == implementor) {
|
|
switch (part_number) {
|
|
case 0xB360: /* ARM1136 */
|
|
case 0xB560: /* ARM1156 */
|
|
case 0xB760: /* ARM1176 */
|
|
armpmu = armv6pmu_init();
|
|
break;
|
|
case 0xB020: /* ARM11mpcore */
|
|
armpmu = armv6mpcore_pmu_init();
|
|
break;
|
|
case 0xC080: /* Cortex-A8 */
|
|
armpmu = armv7_a8_pmu_init();
|
|
break;
|
|
case 0xC090: /* Cortex-A9 */
|
|
armpmu = armv7_a9_pmu_init();
|
|
break;
|
|
}
|
|
/* Intel CPUs [xscale]. */
|
|
} else if (0x69 == implementor) {
|
|
part_number = (cpuid >> 13) & 0x7;
|
|
switch (part_number) {
|
|
case 1:
|
|
armpmu = xscale1pmu_init();
|
|
break;
|
|
case 2:
|
|
armpmu = xscale2pmu_init();
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (armpmu) {
|
|
pr_info("enabled with %s PMU driver, %d counters available\n",
|
|
armpmu->name, armpmu->num_events);
|
|
} else {
|
|
pr_info("no hardware support available\n");
|
|
}
|
|
|
|
perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(init_hw_perf_events);
|
|
|
|
/*
|
|
* Callchain handling code.
|
|
*/
|
|
|
|
/*
|
|
* The registers we're interested in are at the end of the variable
|
|
* length saved register structure. The fp points at the end of this
|
|
* structure so the address of this struct is:
|
|
* (struct frame_tail *)(xxx->fp)-1
|
|
*
|
|
* This code has been adapted from the ARM OProfile support.
|
|
*/
|
|
struct frame_tail {
|
|
struct frame_tail __user *fp;
|
|
unsigned long sp;
|
|
unsigned long lr;
|
|
} __attribute__((packed));
|
|
|
|
/*
|
|
* Get the return address for a single stackframe and return a pointer to the
|
|
* next frame tail.
|
|
*/
|
|
static struct frame_tail __user *
|
|
user_backtrace(struct frame_tail __user *tail,
|
|
struct perf_callchain_entry *entry)
|
|
{
|
|
struct frame_tail buftail;
|
|
|
|
/* Also check accessibility of one struct frame_tail beyond */
|
|
if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
|
|
return NULL;
|
|
if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
|
|
return NULL;
|
|
|
|
perf_callchain_store(entry, buftail.lr);
|
|
|
|
/*
|
|
* Frame pointers should strictly progress back up the stack
|
|
* (towards higher addresses).
|
|
*/
|
|
if (tail + 1 >= buftail.fp)
|
|
return NULL;
|
|
|
|
return buftail.fp - 1;
|
|
}
|
|
|
|
void
|
|
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
|
|
{
|
|
struct frame_tail __user *tail;
|
|
|
|
|
|
tail = (struct frame_tail __user *)regs->ARM_fp - 1;
|
|
|
|
while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
|
|
tail && !((unsigned long)tail & 0x3))
|
|
tail = user_backtrace(tail, entry);
|
|
}
|
|
|
|
/*
|
|
* Gets called by walk_stackframe() for every stackframe. This will be called
|
|
* whist unwinding the stackframe and is like a subroutine return so we use
|
|
* the PC.
|
|
*/
|
|
static int
|
|
callchain_trace(struct stackframe *fr,
|
|
void *data)
|
|
{
|
|
struct perf_callchain_entry *entry = data;
|
|
perf_callchain_store(entry, fr->pc);
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
|
|
{
|
|
struct stackframe fr;
|
|
|
|
fr.fp = regs->ARM_fp;
|
|
fr.sp = regs->ARM_sp;
|
|
fr.lr = regs->ARM_lr;
|
|
fr.pc = regs->ARM_pc;
|
|
walk_stackframe(&fr, callchain_trace, entry);
|
|
}
|