![Seungwhan Youn](/assets/img/avatar_default.png)
S5P Samsung SoCs has a EPLL to support various PLL clock sources for other H/W blocks. Until now, to control EPLL, each of SoCs make their own functions in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and 'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move these duplicated codes to common EPLL functions that use platform wide. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
236 lines
5.3 KiB
C
236 lines
5.3 KiB
C
/* linux/arch/arm/mach-s5p64x0/clock.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5P64X0 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/sysdev.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/s5p6440.h>
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#include <plat/s5p6450.h>
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struct clksrc_clk clk_mout_apll = {
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.clk = {
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.name = "mout_apll",
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.id = -1,
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},
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
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};
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struct clksrc_clk clk_mout_mpll = {
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.clk = {
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.name = "mout_mpll",
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.id = -1,
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},
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.sources = &clk_src_mpll,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
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};
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struct clksrc_clk clk_mout_epll = {
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.clk = {
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.name = "mout_epll",
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.id = -1,
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},
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.sources = &clk_src_epll,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
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};
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enum perf_level {
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L0 = 532*1000,
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L1 = 266*1000,
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L2 = 133*1000,
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};
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static const u32 clock_table[][3] = {
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/*{ARM_CLK, DIVarm, DIVhclk}*/
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{L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
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{L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
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{L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
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};
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unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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u32 clkdiv;
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/* divisor mask starts at bit0, so no need to shift */
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clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
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return rate / (clkdiv + 1);
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}
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unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
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{
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u32 iter;
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for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
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if (rate > clock_table[iter][0])
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return clock_table[iter-1][0];
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}
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return clock_table[ARRAY_SIZE(clock_table) - 1][0];
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}
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int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 round_tmp;
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u32 iter;
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u32 clk_div0_tmp;
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u32 cur_rate = clk->ops->get_rate(clk);
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unsigned long flags;
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round_tmp = clk->ops->round_rate(clk, rate);
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if (round_tmp == cur_rate)
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return 0;
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for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
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if (round_tmp == clock_table[iter][0])
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break;
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}
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if (iter >= ARRAY_SIZE(clock_table))
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iter = ARRAY_SIZE(clock_table) - 1;
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local_irq_save(flags);
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if (cur_rate > round_tmp) {
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/* Frequency Down */
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clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
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clk_div0_tmp |= clock_table[iter][1];
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__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
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clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
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~(S5P64X0_CLKDIV0_HCLK_MASK);
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clk_div0_tmp |= clock_table[iter][2];
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__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
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} else {
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/* Frequency Up */
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clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
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~(S5P64X0_CLKDIV0_HCLK_MASK);
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clk_div0_tmp |= clock_table[iter][2];
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__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
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clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
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clk_div0_tmp |= clock_table[iter][1];
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__raw_writel(clk_div0_tmp, ARM_CLK_DIV);
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}
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local_irq_restore(flags);
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clk->rate = clock_table[iter][0];
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return 0;
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}
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struct clk_ops s5p64x0_clkarm_ops = {
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.get_rate = s5p64x0_armclk_get_rate,
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.set_rate = s5p64x0_armclk_set_rate,
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.round_rate = s5p64x0_armclk_round_rate,
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};
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struct clksrc_clk clk_armclk = {
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.clk = {
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.name = "armclk",
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.id = 1,
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.parent = &clk_mout_apll.clk,
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.ops = &s5p64x0_clkarm_ops,
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},
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.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
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};
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struct clksrc_clk clk_dout_mpll = {
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.clk = {
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.name = "dout_mpll",
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.id = -1,
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.parent = &clk_mout_mpll.clk,
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},
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.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
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};
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struct clk *clkset_hclk_low_list[] = {
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&clk_mout_apll.clk,
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&clk_mout_mpll.clk,
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};
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struct clksrc_sources clkset_hclk_low = {
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.sources = clkset_hclk_low_list,
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.nr_sources = ARRAY_SIZE(clkset_hclk_low_list),
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};
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int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
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}
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int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
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}
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int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
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}
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int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
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}
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int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
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}
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int s5p64x0_mem_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
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}
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int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
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{
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unsigned long flags;
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u32 val;
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/* can't rely on clock lock, this register has other usages */
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local_irq_save(flags);
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val = __raw_readl(S5P64X0_OTHERS);
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if (enable)
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val |= S5P64X0_OTHERS_USB_SIG_MASK;
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else
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val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
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__raw_writel(val, S5P64X0_OTHERS);
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local_irq_restore(flags);
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return 0;
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}
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