![viresh kumar](/assets/img/avatar_default.png)
Define common clk_init routine in plat/clock.c for calling recalc_root_clocks. This routine will be used for any common code across all machine families. Whereas family specific spear*xx_clk_init routines will be used for family specific code. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
683 lines
16 KiB
C
683 lines
16 KiB
C
/*
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* arch/arm/mach-spear6xx/clock.c
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*
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* SPEAr6xx machines clock framework source file
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <plat/clock.h>
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#include <mach/misc_regs.h>
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/* root clks */
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/* 32 KHz oscillator clock */
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static struct clk osc_32k_clk = {
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.flags = ALWAYS_ENABLED,
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.rate = 32000,
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};
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/* 30 MHz oscillator clock */
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static struct clk osc_30m_clk = {
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.flags = ALWAYS_ENABLED,
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.rate = 30000000,
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};
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/* clock derived from 32 KHz osc clk */
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/* rtc clock */
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static struct clk rtc_clk = {
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.pclk = &osc_32k_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = RTC_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* clock derived from 30 MHz osc clk */
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/* pll masks structure */
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static struct pll_clk_masks pll1_masks = {
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.mode_mask = PLL_MODE_MASK,
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.mode_shift = PLL_MODE_SHIFT,
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.norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
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.norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
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.dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
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.dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
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.div_p_mask = PLL_DIV_P_MASK,
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.div_p_shift = PLL_DIV_P_SHIFT,
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.div_n_mask = PLL_DIV_N_MASK,
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.div_n_shift = PLL_DIV_N_SHIFT,
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};
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/* pll1 configuration structure */
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static struct pll_clk_config pll1_config = {
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.mode_reg = PLL1_CTR,
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.cfg_reg = PLL1_FRQ,
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.masks = &pll1_masks,
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};
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/* pll rate configuration table, in ascending order of rates */
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struct pll_rate_tbl pll_rtbl[] = {
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{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
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{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
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};
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/* PLL1 clock */
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static struct clk pll1_clk = {
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.flags = ENABLED_ON_INIT,
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.pclk = &osc_30m_clk,
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.en_reg = PLL1_CTR,
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.en_reg_bit = PLL_ENABLE,
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.calc_rate = &pll_calc_rate,
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.recalc = &pll_clk_recalc,
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.set_rate = &pll_clk_set_rate,
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.rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
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.private_data = &pll1_config,
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};
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/* PLL3 48 MHz clock */
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static struct clk pll3_48m_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &osc_30m_clk,
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.rate = 48000000,
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};
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/* watch dog timer clock */
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static struct clk wdt_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &osc_30m_clk,
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.recalc = &follow_parent,
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};
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/* clock derived from pll1 clk */
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/* cpu clock */
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static struct clk cpu_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &pll1_clk,
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.recalc = &follow_parent,
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};
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/* ahb masks structure */
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static struct bus_clk_masks ahb_masks = {
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.mask = PLL_HCLK_RATIO_MASK,
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.shift = PLL_HCLK_RATIO_SHIFT,
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};
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/* ahb configuration structure */
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static struct bus_clk_config ahb_config = {
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.reg = CORE_CLK_CFG,
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.masks = &ahb_masks,
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};
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/* ahb rate configuration table, in ascending order of rates */
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struct bus_rate_tbl bus_rtbl[] = {
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{.div = 3}, /* == parent divided by 4 */
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{.div = 2}, /* == parent divided by 3 */
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{.div = 1}, /* == parent divided by 2 */
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{.div = 0}, /* == parent divided by 1 */
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};
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/* ahb clock */
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static struct clk ahb_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &pll1_clk,
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.calc_rate = &bus_calc_rate,
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.recalc = &bus_clk_recalc,
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.set_rate = &bus_clk_set_rate,
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.rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
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.private_data = &ahb_config,
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};
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/* auxiliary synthesizers masks */
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static struct aux_clk_masks aux_masks = {
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.eq_sel_mask = AUX_EQ_SEL_MASK,
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.eq_sel_shift = AUX_EQ_SEL_SHIFT,
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.eq1_mask = AUX_EQ1_SEL,
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.eq2_mask = AUX_EQ2_SEL,
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.xscale_sel_mask = AUX_XSCALE_MASK,
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.xscale_sel_shift = AUX_XSCALE_SHIFT,
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.yscale_sel_mask = AUX_YSCALE_MASK,
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.yscale_sel_shift = AUX_YSCALE_SHIFT,
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};
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/* uart configurations */
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static struct aux_clk_config uart_synth_config = {
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.synth_reg = UART_CLK_SYNT,
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.masks = &aux_masks,
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};
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/* aux rate configuration table, in ascending order of rates */
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struct aux_rate_tbl aux_rtbl[] = {
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/* For PLL1 = 332 MHz */
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{.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
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{.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
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{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
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};
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/* uart synth clock */
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static struct clk uart_synth_clk = {
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.en_reg = UART_CLK_SYNT,
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.en_reg_bit = AUX_SYNT_ENB,
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.pclk = &pll1_clk,
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.calc_rate = &aux_calc_rate,
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.recalc = &aux_clk_recalc,
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.set_rate = &aux_clk_set_rate,
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.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
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.private_data = &uart_synth_config,
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};
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/* uart parents */
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static struct pclk_info uart_pclk_info[] = {
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{
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.pclk = &uart_synth_clk,
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.pclk_val = AUX_CLK_PLL1_VAL,
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}, {
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.pclk = &pll3_48m_clk,
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.pclk_val = AUX_CLK_PLL3_VAL,
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},
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};
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/* uart parent select structure */
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static struct pclk_sel uart_pclk_sel = {
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.pclk_info = uart_pclk_info,
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.pclk_count = ARRAY_SIZE(uart_pclk_info),
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.pclk_sel_reg = PERIP_CLK_CFG,
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.pclk_sel_mask = UART_CLK_MASK,
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};
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/* uart0 clock */
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static struct clk uart0_clk = {
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = UART0_CLK_ENB,
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.pclk_sel = &uart_pclk_sel,
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.pclk_sel_shift = UART_CLK_SHIFT,
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.recalc = &follow_parent,
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};
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/* uart1 clock */
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static struct clk uart1_clk = {
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = UART1_CLK_ENB,
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.pclk_sel = &uart_pclk_sel,
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.pclk_sel_shift = UART_CLK_SHIFT,
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.recalc = &follow_parent,
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};
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/* firda configurations */
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static struct aux_clk_config firda_synth_config = {
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.synth_reg = FIRDA_CLK_SYNT,
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.masks = &aux_masks,
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};
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/* firda synth clock */
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static struct clk firda_synth_clk = {
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.en_reg = FIRDA_CLK_SYNT,
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.en_reg_bit = AUX_SYNT_ENB,
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.pclk = &pll1_clk,
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.calc_rate = &aux_calc_rate,
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.recalc = &aux_clk_recalc,
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.set_rate = &aux_clk_set_rate,
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.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
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.private_data = &firda_synth_config,
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};
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/* firda parents */
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static struct pclk_info firda_pclk_info[] = {
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{
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.pclk = &firda_synth_clk,
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.pclk_val = AUX_CLK_PLL1_VAL,
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}, {
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.pclk = &pll3_48m_clk,
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.pclk_val = AUX_CLK_PLL3_VAL,
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},
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};
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/* firda parent select structure */
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static struct pclk_sel firda_pclk_sel = {
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.pclk_info = firda_pclk_info,
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.pclk_count = ARRAY_SIZE(firda_pclk_info),
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.pclk_sel_reg = PERIP_CLK_CFG,
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.pclk_sel_mask = FIRDA_CLK_MASK,
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};
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/* firda clock */
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static struct clk firda_clk = {
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = FIRDA_CLK_ENB,
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.pclk_sel = &firda_pclk_sel,
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.pclk_sel_shift = FIRDA_CLK_SHIFT,
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.recalc = &follow_parent,
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};
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/* clcd configurations */
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static struct aux_clk_config clcd_synth_config = {
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.synth_reg = CLCD_CLK_SYNT,
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.masks = &aux_masks,
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};
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/* firda synth clock */
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static struct clk clcd_synth_clk = {
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.en_reg = CLCD_CLK_SYNT,
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.en_reg_bit = AUX_SYNT_ENB,
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.pclk = &pll1_clk,
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.calc_rate = &aux_calc_rate,
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.recalc = &aux_clk_recalc,
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.set_rate = &aux_clk_set_rate,
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.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
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.private_data = &clcd_synth_config,
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};
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/* clcd parents */
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static struct pclk_info clcd_pclk_info[] = {
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{
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.pclk = &clcd_synth_clk,
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.pclk_val = AUX_CLK_PLL1_VAL,
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}, {
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.pclk = &pll3_48m_clk,
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.pclk_val = AUX_CLK_PLL3_VAL,
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},
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};
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/* clcd parent select structure */
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static struct pclk_sel clcd_pclk_sel = {
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.pclk_info = clcd_pclk_info,
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.pclk_count = ARRAY_SIZE(clcd_pclk_info),
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.pclk_sel_reg = PERIP_CLK_CFG,
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.pclk_sel_mask = CLCD_CLK_MASK,
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};
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/* clcd clock */
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static struct clk clcd_clk = {
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = CLCD_CLK_ENB,
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.pclk_sel = &clcd_pclk_sel,
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.pclk_sel_shift = CLCD_CLK_SHIFT,
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.recalc = &follow_parent,
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};
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/* gpt synthesizer masks */
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static struct gpt_clk_masks gpt_masks = {
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.mscale_sel_mask = GPT_MSCALE_MASK,
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.mscale_sel_shift = GPT_MSCALE_SHIFT,
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.nscale_sel_mask = GPT_NSCALE_MASK,
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.nscale_sel_shift = GPT_NSCALE_SHIFT,
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};
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/* gpt rate configuration table, in ascending order of rates */
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struct gpt_rate_tbl gpt_rtbl[] = {
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/* For pll1 = 332 MHz */
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{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
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{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
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{.mscale = 1, .nscale = 0}, /* 83 MHz */
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};
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/* gpt0 synth clk config*/
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static struct gpt_clk_config gpt0_synth_config = {
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.synth_reg = PRSC1_CLK_CFG,
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.masks = &gpt_masks,
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};
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/* gpt synth clock */
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static struct clk gpt0_synth_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &pll1_clk,
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.calc_rate = &gpt_calc_rate,
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.recalc = &gpt_clk_recalc,
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.set_rate = &gpt_clk_set_rate,
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.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
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.private_data = &gpt0_synth_config,
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};
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/* gpt parents */
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static struct pclk_info gpt0_pclk_info[] = {
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{
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.pclk = &gpt0_synth_clk,
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.pclk_val = AUX_CLK_PLL1_VAL,
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}, {
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.pclk = &pll3_48m_clk,
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.pclk_val = AUX_CLK_PLL3_VAL,
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},
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};
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/* gpt parent select structure */
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static struct pclk_sel gpt0_pclk_sel = {
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.pclk_info = gpt0_pclk_info,
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.pclk_count = ARRAY_SIZE(gpt0_pclk_info),
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.pclk_sel_reg = PERIP_CLK_CFG,
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.pclk_sel_mask = GPT_CLK_MASK,
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};
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/* gpt0 ARM1 subsystem timer clock */
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static struct clk gpt0_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk_sel = &gpt0_pclk_sel,
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.pclk_sel_shift = GPT0_CLK_SHIFT,
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.recalc = &follow_parent,
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};
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/* Note: gpt0 and gpt1 share same parent clocks */
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/* gpt parent select structure */
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static struct pclk_sel gpt1_pclk_sel = {
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.pclk_info = gpt0_pclk_info,
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.pclk_count = ARRAY_SIZE(gpt0_pclk_info),
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.pclk_sel_reg = PERIP_CLK_CFG,
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.pclk_sel_mask = GPT_CLK_MASK,
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};
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/* gpt1 timer clock */
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static struct clk gpt1_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk_sel = &gpt1_pclk_sel,
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.pclk_sel_shift = GPT1_CLK_SHIFT,
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.recalc = &follow_parent,
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};
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/* gpt2 synth clk config*/
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static struct gpt_clk_config gpt2_synth_config = {
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.synth_reg = PRSC2_CLK_CFG,
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.masks = &gpt_masks,
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};
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/* gpt synth clock */
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static struct clk gpt2_synth_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &pll1_clk,
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.calc_rate = &gpt_calc_rate,
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.recalc = &gpt_clk_recalc,
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.set_rate = &gpt_clk_set_rate,
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.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
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.private_data = &gpt2_synth_config,
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};
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/* gpt parents */
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static struct pclk_info gpt2_pclk_info[] = {
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{
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.pclk = &gpt2_synth_clk,
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.pclk_val = AUX_CLK_PLL1_VAL,
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}, {
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.pclk = &pll3_48m_clk,
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.pclk_val = AUX_CLK_PLL3_VAL,
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},
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};
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/* gpt parent select structure */
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static struct pclk_sel gpt2_pclk_sel = {
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.pclk_info = gpt2_pclk_info,
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.pclk_count = ARRAY_SIZE(gpt2_pclk_info),
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.pclk_sel_reg = PERIP_CLK_CFG,
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.pclk_sel_mask = GPT_CLK_MASK,
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};
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/* gpt2 timer clock */
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static struct clk gpt2_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk_sel = &gpt2_pclk_sel,
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.pclk_sel_shift = GPT2_CLK_SHIFT,
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.recalc = &follow_parent,
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};
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/* gpt3 synth clk config*/
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static struct gpt_clk_config gpt3_synth_config = {
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.synth_reg = PRSC3_CLK_CFG,
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.masks = &gpt_masks,
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};
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/* gpt synth clock */
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static struct clk gpt3_synth_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &pll1_clk,
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.calc_rate = &gpt_calc_rate,
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.recalc = &gpt_clk_recalc,
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.set_rate = &gpt_clk_set_rate,
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.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
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.private_data = &gpt3_synth_config,
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};
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/* gpt parents */
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static struct pclk_info gpt3_pclk_info[] = {
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{
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.pclk = &gpt3_synth_clk,
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.pclk_val = AUX_CLK_PLL1_VAL,
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}, {
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.pclk = &pll3_48m_clk,
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.pclk_val = AUX_CLK_PLL3_VAL,
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},
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};
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/* gpt parent select structure */
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static struct pclk_sel gpt3_pclk_sel = {
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.pclk_info = gpt3_pclk_info,
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.pclk_count = ARRAY_SIZE(gpt3_pclk_info),
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.pclk_sel_reg = PERIP_CLK_CFG,
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.pclk_sel_mask = GPT_CLK_MASK,
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};
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/* gpt3 timer clock */
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static struct clk gpt3_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk_sel = &gpt3_pclk_sel,
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.pclk_sel_shift = GPT3_CLK_SHIFT,
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.recalc = &follow_parent,
|
|
};
|
|
|
|
/* clock derived from pll3 clk */
|
|
/* usbh0 clock */
|
|
static struct clk usbh0_clk = {
|
|
.pclk = &pll3_48m_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = USBH0_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* usbh1 clock */
|
|
static struct clk usbh1_clk = {
|
|
.pclk = &pll3_48m_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = USBH1_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* usbd clock */
|
|
static struct clk usbd_clk = {
|
|
.pclk = &pll3_48m_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = USBD_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* clock derived from ahb clk */
|
|
/* apb masks structure */
|
|
static struct bus_clk_masks apb_masks = {
|
|
.mask = HCLK_PCLK_RATIO_MASK,
|
|
.shift = HCLK_PCLK_RATIO_SHIFT,
|
|
};
|
|
|
|
/* apb configuration structure */
|
|
static struct bus_clk_config apb_config = {
|
|
.reg = CORE_CLK_CFG,
|
|
.masks = &apb_masks,
|
|
};
|
|
|
|
/* apb clock */
|
|
static struct clk apb_clk = {
|
|
.flags = ALWAYS_ENABLED,
|
|
.pclk = &ahb_clk,
|
|
.calc_rate = &bus_calc_rate,
|
|
.recalc = &bus_clk_recalc,
|
|
.set_rate = &bus_clk_set_rate,
|
|
.rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
|
|
.private_data = &apb_config,
|
|
};
|
|
|
|
/* i2c clock */
|
|
static struct clk i2c_clk = {
|
|
.pclk = &ahb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = I2C_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* dma clock */
|
|
static struct clk dma_clk = {
|
|
.pclk = &ahb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = DMA_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* jpeg clock */
|
|
static struct clk jpeg_clk = {
|
|
.pclk = &ahb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = JPEG_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* gmac clock */
|
|
static struct clk gmac_clk = {
|
|
.pclk = &ahb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = GMAC_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* smi clock */
|
|
static struct clk smi_clk = {
|
|
.pclk = &ahb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = SMI_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* fsmc clock */
|
|
static struct clk fsmc_clk = {
|
|
.pclk = &ahb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = FSMC_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* clock derived from apb clk */
|
|
/* adc clock */
|
|
static struct clk adc_clk = {
|
|
.pclk = &apb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = ADC_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* ssp0 clock */
|
|
static struct clk ssp0_clk = {
|
|
.pclk = &apb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = SSP0_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* ssp1 clock */
|
|
static struct clk ssp1_clk = {
|
|
.pclk = &apb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = SSP1_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* ssp2 clock */
|
|
static struct clk ssp2_clk = {
|
|
.pclk = &apb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = SSP2_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* gpio0 ARM subsystem clock */
|
|
static struct clk gpio0_clk = {
|
|
.flags = ALWAYS_ENABLED,
|
|
.pclk = &apb_clk,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* gpio1 clock */
|
|
static struct clk gpio1_clk = {
|
|
.pclk = &apb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = GPIO1_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
/* gpio2 clock */
|
|
static struct clk gpio2_clk = {
|
|
.pclk = &apb_clk,
|
|
.en_reg = PERIP1_CLK_ENB,
|
|
.en_reg_bit = GPIO2_CLK_ENB,
|
|
.recalc = &follow_parent,
|
|
};
|
|
|
|
static struct clk dummy_apb_pclk;
|
|
|
|
/* array of all spear 6xx clock lookups */
|
|
static struct clk_lookup spear_clk_lookups[] = {
|
|
{ .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
|
|
/* root clks */
|
|
{ .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
|
|
{ .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
|
|
/* clock derived from 32 KHz os clk */
|
|
{ .dev_id = "rtc-spear", .clk = &rtc_clk},
|
|
/* clock derived from 30 MHz os clk */
|
|
{ .con_id = "pll1_clk", .clk = &pll1_clk},
|
|
{ .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
|
|
{ .dev_id = "wdt", .clk = &wdt_clk},
|
|
/* clock derived from pll1 clk */
|
|
{ .con_id = "cpu_clk", .clk = &cpu_clk},
|
|
{ .con_id = "ahb_clk", .clk = &ahb_clk},
|
|
{ .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
|
|
{ .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
|
|
{ .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
|
|
{ .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
|
|
{ .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
|
|
{ .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk},
|
|
{ .dev_id = "uart0", .clk = &uart0_clk},
|
|
{ .dev_id = "uart1", .clk = &uart1_clk},
|
|
{ .dev_id = "firda", .clk = &firda_clk},
|
|
{ .dev_id = "clcd", .clk = &clcd_clk},
|
|
{ .dev_id = "gpt0", .clk = &gpt0_clk},
|
|
{ .dev_id = "gpt1", .clk = &gpt1_clk},
|
|
{ .dev_id = "gpt2", .clk = &gpt2_clk},
|
|
{ .dev_id = "gpt3", .clk = &gpt3_clk},
|
|
/* clock derived from pll3 clk */
|
|
{ .dev_id = "designware_udc", .clk = &usbd_clk},
|
|
{ .con_id = "usbh.0_clk", .clk = &usbh0_clk},
|
|
{ .con_id = "usbh.1_clk", .clk = &usbh1_clk},
|
|
/* clock derived from ahb clk */
|
|
{ .con_id = "apb_clk", .clk = &apb_clk},
|
|
{ .dev_id = "i2c_designware.0", .clk = &i2c_clk},
|
|
{ .dev_id = "dma", .clk = &dma_clk},
|
|
{ .dev_id = "jpeg", .clk = &jpeg_clk},
|
|
{ .dev_id = "gmac", .clk = &gmac_clk},
|
|
{ .dev_id = "smi", .clk = &smi_clk},
|
|
{ .con_id = "fsmc", .clk = &fsmc_clk},
|
|
/* clock derived from apb clk */
|
|
{ .dev_id = "adc", .clk = &adc_clk},
|
|
{ .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
|
|
{ .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
|
|
{ .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
|
|
{ .dev_id = "gpio0", .clk = &gpio0_clk},
|
|
{ .dev_id = "gpio1", .clk = &gpio1_clk},
|
|
{ .dev_id = "gpio2", .clk = &gpio2_clk},
|
|
};
|
|
|
|
void __init spear6xx_clk_init(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
|
|
clk_register(&spear_clk_lookups[i]);
|
|
|
|
clk_init();
|
|
}
|