![Linus Torvalds](/assets/img/avatar_default.png)
Pull irq updates from Thomas Gleixner: "This is a rather large update post rc1 due to the final steps of cleanups and API changes which had to wait for the preparatory patches to hit your tree. - Regression fixes for ARM GIC irqchips - Regression fixes and lockdep anotations for renesas irq chips - The leftovers of the cleanup and preparatory patches which have been ignored by maintainers - Final conversions of the newly merged users of obsolete APIs - Final removal of obsolete APIs - Final removal of ARM artifacts which had been introduced during the conversion of ARM to the generic interrupt code. - Final split of the irq_data into chip specific and common data to reflect the needs of hierarchical irq domains. - Treewide removal of the first argument of interrupt flow handlers, i.e. the irq number, which is not used by the majority of handlers and simple to retrieve from the other argument the irq descriptor. - A few comment updates and build warning fixes" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (40 commits) arm64: Remove ununsed set_irq_flags ARM: Remove ununsed set_irq_flags sh: Kill off set_irq_flags usage irqchip: Kill off set_irq_flags usage gpu/drm: Kill off set_irq_flags usage genirq: Remove irq argument from irq flow handlers genirq: Move field 'msi_desc' from irq_data into irq_common_data genirq: Move field 'affinity' from irq_data into irq_common_data genirq: Move field 'handler_data' from irq_data into irq_common_data genirq: Move field 'node' from irq_data into irq_common_data irqchip/gic-v3: Use IRQD_FORWARDED_TO_VCPU flag irqchip/gic: Use IRQD_FORWARDED_TO_VCPU flag genirq: Provide IRQD_FORWARDED_TO_VCPU status flag genirq: Simplify irq_data_to_desc() genirq: Remove __irq_set_handler_locked() pinctrl/pistachio: Use irq_set_handler_locked gpio: vf610: Use irq_set_handler_locked powerpc/mpc8xx: Use irq_set_handler_locked() powerpc/ipic: Use irq_set_handler_locked() powerpc/cpm2: Use irq_set_handler_locked() ...
380 lines
9.9 KiB
C
380 lines
9.9 KiB
C
/*
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* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* Based on code from Freescale,
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* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/gpio.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/basic_mmio_gpio.h>
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#include <linux/module.h>
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#define MXS_SET 0x4
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#define MXS_CLR 0x8
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#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
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#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
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#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
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#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
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#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
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#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
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#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
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#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
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#define GPIO_INT_FALL_EDGE 0x0
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#define GPIO_INT_LOW_LEV 0x1
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#define GPIO_INT_RISE_EDGE 0x2
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#define GPIO_INT_HIGH_LEV 0x3
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#define GPIO_INT_LEV_MASK (1 << 0)
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#define GPIO_INT_POL_MASK (1 << 1)
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enum mxs_gpio_id {
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IMX23_GPIO,
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IMX28_GPIO,
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};
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struct mxs_gpio_port {
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void __iomem *base;
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int id;
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int irq;
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struct irq_domain *domain;
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struct bgpio_chip bgc;
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enum mxs_gpio_id devid;
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u32 both_edges;
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};
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static inline int is_imx23_gpio(struct mxs_gpio_port *port)
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{
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return port->devid == IMX23_GPIO;
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}
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static inline int is_imx28_gpio(struct mxs_gpio_port *port)
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{
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return port->devid == IMX28_GPIO;
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}
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/* Note: This driver assumes 32 GPIOs are handled in one register */
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static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
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{
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u32 val;
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u32 pin_mask = 1 << d->hwirq;
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mxs_gpio_port *port = gc->private;
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void __iomem *pin_addr;
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int edge;
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port->both_edges &= ~pin_mask;
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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val = gpio_get_value(port->bgc.gc.base + d->hwirq);
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if (val)
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edge = GPIO_INT_FALL_EDGE;
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else
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edge = GPIO_INT_RISE_EDGE;
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port->both_edges |= pin_mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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edge = GPIO_INT_RISE_EDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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edge = GPIO_INT_FALL_EDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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edge = GPIO_INT_LOW_LEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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edge = GPIO_INT_HIGH_LEV;
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break;
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default:
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return -EINVAL;
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}
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/* set level or edge */
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pin_addr = port->base + PINCTRL_IRQLEV(port);
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if (edge & GPIO_INT_LEV_MASK)
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writel(pin_mask, pin_addr + MXS_SET);
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else
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writel(pin_mask, pin_addr + MXS_CLR);
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/* set polarity */
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pin_addr = port->base + PINCTRL_IRQPOL(port);
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if (edge & GPIO_INT_POL_MASK)
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writel(pin_mask, pin_addr + MXS_SET);
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else
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writel(pin_mask, pin_addr + MXS_CLR);
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writel(pin_mask,
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port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
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return 0;
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}
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static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
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{
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u32 bit, val, edge;
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void __iomem *pin_addr;
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bit = 1 << gpio;
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pin_addr = port->base + PINCTRL_IRQPOL(port);
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val = readl(pin_addr);
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edge = val & bit;
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if (edge)
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writel(bit, pin_addr + MXS_CLR);
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else
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writel(bit, pin_addr + MXS_SET);
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}
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/* MXS has one interrupt *per* gpio port */
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static void mxs_gpio_irq_handler(struct irq_desc *desc)
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{
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u32 irq_stat;
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struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
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readl(port->base + PINCTRL_IRQEN(port));
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while (irq_stat != 0) {
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int irqoffset = fls(irq_stat) - 1;
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if (port->both_edges & (1 << irqoffset))
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mxs_flip_edge(port, irqoffset);
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generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
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irq_stat &= ~(1 << irqoffset);
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}
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}
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/*
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* Set interrupt number "irq" in the GPIO as a wake-up source.
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* While system is running, all registered GPIO interrupts need to have
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* wake-up enabled. When system is suspended, only selected GPIO interrupts
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* need to have wake-up enabled.
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* @param irq interrupt source number
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* @param enable enable as wake-up if equal to non-zero
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* @return This function returns 0 on success.
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*/
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static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mxs_gpio_port *port = gc->private;
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if (enable)
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enable_irq_wake(port->irq);
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else
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disable_irq_wake(port->irq);
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return 0;
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}
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static int __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
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port->base, handle_level_irq);
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if (!gc)
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return -ENOMEM;
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gc->private = port;
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = mxs_gpio_set_irq_type;
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ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
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ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
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ct->regs.mask = PINCTRL_IRQEN(port);
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irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
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IRQ_NOREQUEST, 0);
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return 0;
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}
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static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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struct mxs_gpio_port *port =
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container_of(bgc, struct mxs_gpio_port, bgc);
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return irq_find_mapping(port->domain, offset);
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}
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static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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struct mxs_gpio_port *port =
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container_of(bgc, struct mxs_gpio_port, bgc);
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u32 mask = 1 << offset;
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u32 dir;
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dir = readl(port->base + PINCTRL_DOE(port));
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return !(dir & mask);
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}
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static const struct platform_device_id mxs_gpio_ids[] = {
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{
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.name = "imx23-gpio",
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.driver_data = IMX23_GPIO,
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}, {
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.name = "imx28-gpio",
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.driver_data = IMX28_GPIO,
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}, {
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/* sentinel */
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}
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};
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MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
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static const struct of_device_id mxs_gpio_dt_ids[] = {
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{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
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{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
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static int mxs_gpio_probe(struct platform_device *pdev)
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{
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const struct of_device_id *of_id =
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of_match_device(mxs_gpio_dt_ids, &pdev->dev);
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struct device_node *np = pdev->dev.of_node;
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struct device_node *parent;
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static void __iomem *base;
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struct mxs_gpio_port *port;
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int irq_base;
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int err;
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port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
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if (!port)
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return -ENOMEM;
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port->id = of_alias_get_id(np, "gpio");
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if (port->id < 0)
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return port->id;
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port->devid = (enum mxs_gpio_id) of_id->data;
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port->irq = platform_get_irq(pdev, 0);
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if (port->irq < 0)
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return port->irq;
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/*
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* map memory region only once, as all the gpio ports
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* share the same one
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*/
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if (!base) {
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parent = of_get_parent(np);
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base = of_iomap(parent, 0);
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of_node_put(parent);
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if (!base)
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return -EADDRNOTAVAIL;
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}
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port->base = base;
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/*
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* select the pin interrupt functionality but initially
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* disable the interrupts
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*/
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writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
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writel(0, port->base + PINCTRL_IRQEN(port));
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/* clear address has to be used to clear IRQSTAT bits */
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writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
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irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
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if (irq_base < 0)
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return irq_base;
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port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (!port->domain) {
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err = -ENODEV;
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goto out_irqdesc_free;
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}
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/* gpio-mxs can be a generic irq chip */
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err = mxs_gpio_init_gc(port, irq_base);
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if (err < 0)
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goto out_irqdomain_remove;
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/* setup one handler for each entry */
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irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
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port);
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err = bgpio_init(&port->bgc, &pdev->dev, 4,
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port->base + PINCTRL_DIN(port),
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port->base + PINCTRL_DOUT(port) + MXS_SET,
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port->base + PINCTRL_DOUT(port) + MXS_CLR,
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port->base + PINCTRL_DOE(port), NULL, 0);
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if (err)
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goto out_irqdesc_free;
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port->bgc.gc.to_irq = mxs_gpio_to_irq;
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port->bgc.gc.get_direction = mxs_gpio_get_direction;
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port->bgc.gc.base = port->id * 32;
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err = gpiochip_add(&port->bgc.gc);
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if (err)
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goto out_bgpio_remove;
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return 0;
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out_bgpio_remove:
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bgpio_remove(&port->bgc);
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out_irqdomain_remove:
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irq_domain_remove(port->domain);
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out_irqdesc_free:
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irq_free_descs(irq_base, 32);
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return err;
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}
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static struct platform_driver mxs_gpio_driver = {
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.driver = {
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.name = "gpio-mxs",
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.of_match_table = mxs_gpio_dt_ids,
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},
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.probe = mxs_gpio_probe,
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.id_table = mxs_gpio_ids,
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};
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static int __init mxs_gpio_init(void)
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{
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return platform_driver_register(&mxs_gpio_driver);
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}
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postcore_initcall(mxs_gpio_init);
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MODULE_AUTHOR("Freescale Semiconductor, "
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"Daniel Mack <danielncaiaq.de>, "
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"Juergen Beisert <kernel@pengutronix.de>");
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MODULE_DESCRIPTION("Freescale MXS GPIO");
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MODULE_LICENSE("GPL");
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