Catalin Marinas 382266ad5a [ARM] 4135/1: Add support for the L210/L220 cache controllers ... This patch adds the support for the L210/L220 (outer) cache controller. The cache range operations are done by index/way since L2 cache controller only accepts physical addresses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>		2007-02-11 16:48:02 +00:00
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arm_scu.h
arm_timer.h
arm_twd.h
cache-l2x0.h	[ARM] 4135/1: Add support for the L210/L220 cache controllers	2007-02-11 16:48:02 +00:00
clps7111.h
cs89712.h
debug-8250.S	fix file specification in comments	2006-10-03 23:01:26 +02:00
debug-pl01x.S	fix file specification in comments	2006-10-03 23:01:26 +02:00
dec21285.h
entry-macro-iomd.S	fix file specification in comments	2006-10-03 23:01:26 +02:00
ep7211.h
ep7212.h
gic.h
icst307.h
icst525.h
ioc.h
iomd.h
iop3xx.h	[ARM] 4082/1: iop3xx: fix iop33x gpio register offset	2007-01-06 12:43:59 +00:00
linkup-l1110.h
locomo.h	[ARM] 3863/1: Add Locomo SPI Device	2006-09-27 20:59:00 +01:00
memc.h
pci_v3.h
sa1111.h	fix file specification in comments	2006-10-03 23:01:26 +02:00
scoop.h
sharpsl_pm.h	Initial blind fixup for arm for irq changes	2006-10-06 10:59:54 -07:00
ssp.h	[ARM] 3760/1: This patch adds timeouts while working with SSP registers. Such timeouts were en	2006-08-27 12:54:56 +01:00
uengine.h
vic.h