e66774dd6f
There are 3 big benefits to suballocating a single big DMA buffer for command submission: 1. Avoid hammering CMA. The old way of allocating and freeing a DMA buffer for each submission was hitting some of the real slow pathes in CMA, as this allocator was not designed for a concurrent small buffers load. 2. Less TLB flushes on IOMMUv2. If a new command buffer is mapped into the GPU address space the MMU TLBs need to be flushed. By having one big buffer statically mapped to the GPU, a lot of those flushes can be avoided. 3. No funky workarounds for GC3000. The FE TLB flush on GC3000 isn't reliable. To work around that we tried to lay out the cmdbufs in the GPU address space in a way to avoid this issue. This hasn't always worked if the address space is crowded. A single statically mapped buffer avoids the erratum completely. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
201 lines
4.8 KiB
C
201 lines
4.8 KiB
C
/*
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* Copyright (C) 2015 Etnaviv Project
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ETNAVIV_GPU_H__
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#define __ETNAVIV_GPU_H__
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include "etnaviv_drv.h"
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struct etnaviv_gem_submit;
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struct etnaviv_vram_mapping;
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struct etnaviv_chip_identity {
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/* Chip model. */
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u32 model;
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/* Revision value.*/
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u32 revision;
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/* Supported feature fields. */
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u32 features;
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/* Supported minor feature fields. */
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u32 minor_features0;
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/* Supported minor feature 1 fields. */
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u32 minor_features1;
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/* Supported minor feature 2 fields. */
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u32 minor_features2;
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/* Supported minor feature 3 fields. */
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u32 minor_features3;
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/* Supported minor feature 4 fields. */
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u32 minor_features4;
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/* Supported minor feature 5 fields. */
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u32 minor_features5;
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/* Number of streams supported. */
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u32 stream_count;
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/* Total number of temporary registers per thread. */
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u32 register_max;
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/* Maximum number of threads. */
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u32 thread_count;
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/* Number of shader cores. */
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u32 shader_core_count;
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/* Size of the vertex cache. */
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u32 vertex_cache_size;
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/* Number of entries in the vertex output buffer. */
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u32 vertex_output_buffer_size;
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/* Number of pixel pipes. */
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u32 pixel_pipes;
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/* Number of instructions. */
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u32 instruction_count;
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/* Number of constants. */
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u32 num_constants;
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/* Buffer size */
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u32 buffer_size;
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/* Number of varyings */
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u8 varyings_count;
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};
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struct etnaviv_event {
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bool used;
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struct dma_fence *fence;
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};
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struct etnaviv_cmdbuf_suballoc;
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struct etnaviv_cmdbuf;
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struct etnaviv_gpu {
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struct drm_device *drm;
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struct device *dev;
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struct mutex lock;
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struct etnaviv_chip_identity identity;
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struct etnaviv_file_private *lastctx;
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bool switch_context;
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/* 'ring'-buffer: */
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struct etnaviv_cmdbuf *buffer;
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int exec_state;
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/* bus base address of memory */
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u32 memory_base;
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/* event management: */
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struct etnaviv_event event[30];
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struct completion event_free;
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spinlock_t event_spinlock;
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/* list of currently in-flight command buffers */
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struct list_head active_cmd_list;
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u32 idle_mask;
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/* Fencing support */
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u32 next_fence;
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u32 active_fence;
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u32 completed_fence;
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u32 retired_fence;
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wait_queue_head_t fence_event;
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u64 fence_context;
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spinlock_t fence_spinlock;
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/* worker for handling active-list retiring: */
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struct work_struct retire_work;
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void __iomem *mmio;
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int irq;
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struct etnaviv_iommu *mmu;
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struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc;
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/* Power Control: */
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struct clk *clk_bus;
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struct clk *clk_core;
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struct clk *clk_shader;
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/* Hang Detction: */
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#define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */
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#define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD)
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struct timer_list hangcheck_timer;
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u32 hangcheck_fence;
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u32 hangcheck_dma_addr;
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struct work_struct recover_work;
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};
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static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
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{
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etnaviv_writel(data, gpu->mmio + reg);
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}
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static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
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{
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return etnaviv_readl(gpu->mmio + reg);
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}
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static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence)
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{
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return fence_after_eq(gpu->completed_fence, fence);
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}
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static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence)
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{
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return fence_after_eq(gpu->retired_fence, fence);
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}
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int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
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int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
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#ifdef CONFIG_DEBUG_FS
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int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
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#endif
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int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
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unsigned int context, bool exclusive);
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void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
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int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
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u32 fence, struct timespec *timeout);
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int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
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struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout);
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int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
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struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf);
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int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
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void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
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int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
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void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
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extern struct platform_driver etnaviv_gpu_driver;
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#endif /* __ETNAVIV_GPU_H__ */
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