![Carlos Palminha](/assets/img/avatar_default.png)
This patch set nukes all the dummy crtc mode_fixup implementations. (made on top of Daniel topic/drm-misc branch) Signed-off-by: Carlos Palminha <palminha@synopsys.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
997 lines
26 KiB
C
997 lines
26 KiB
C
/*
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* Copyright © 2006-2011 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*/
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#include <linux/i2c.h>
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#include <drm/drmP.h>
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#include "framebuffer.h"
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#include "psb_drv.h"
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#include "psb_intel_drv.h"
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#include "psb_intel_reg.h"
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#include "gma_display.h"
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#include "power.h"
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#include "cdv_device.h"
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static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
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struct drm_crtc *crtc, int target,
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int refclk, struct gma_clock_t *best_clock);
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#define CDV_LIMIT_SINGLE_LVDS_96 0
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#define CDV_LIMIT_SINGLE_LVDS_100 1
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#define CDV_LIMIT_DAC_HDMI_27 2
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#define CDV_LIMIT_DAC_HDMI_96 3
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#define CDV_LIMIT_DP_27 4
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#define CDV_LIMIT_DP_100 5
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static const struct gma_limit_t cdv_intel_limits[] = {
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{ /* CDV_SINGLE_LVDS_96MHz */
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.dot = {.min = 20000, .max = 115500},
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.vco = {.min = 1800000, .max = 3600000},
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.n = {.min = 2, .max = 6},
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.m = {.min = 60, .max = 160},
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.m1 = {.min = 0, .max = 0},
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.m2 = {.min = 58, .max = 158},
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.p = {.min = 28, .max = 140},
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.p1 = {.min = 2, .max = 10},
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.p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
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.find_pll = gma_find_best_pll,
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},
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{ /* CDV_SINGLE_LVDS_100MHz */
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.dot = {.min = 20000, .max = 115500},
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.vco = {.min = 1800000, .max = 3600000},
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.n = {.min = 2, .max = 6},
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.m = {.min = 60, .max = 160},
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.m1 = {.min = 0, .max = 0},
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.m2 = {.min = 58, .max = 158},
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.p = {.min = 28, .max = 140},
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.p1 = {.min = 2, .max = 10},
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/* The single-channel range is 25-112Mhz, and dual-channel
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* is 80-224Mhz. Prefer single channel as much as possible.
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*/
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.p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
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.find_pll = gma_find_best_pll,
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},
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{ /* CDV_DAC_HDMI_27MHz */
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.dot = {.min = 20000, .max = 400000},
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.vco = {.min = 1809000, .max = 3564000},
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.n = {.min = 1, .max = 1},
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.m = {.min = 67, .max = 132},
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.m1 = {.min = 0, .max = 0},
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.m2 = {.min = 65, .max = 130},
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.p = {.min = 5, .max = 90},
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.p1 = {.min = 1, .max = 9},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
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.find_pll = gma_find_best_pll,
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},
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{ /* CDV_DAC_HDMI_96MHz */
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.dot = {.min = 20000, .max = 400000},
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.vco = {.min = 1800000, .max = 3600000},
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.n = {.min = 2, .max = 6},
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.m = {.min = 60, .max = 160},
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.m1 = {.min = 0, .max = 0},
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.m2 = {.min = 58, .max = 158},
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.p = {.min = 5, .max = 100},
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.p1 = {.min = 1, .max = 10},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
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.find_pll = gma_find_best_pll,
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},
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{ /* CDV_DP_27MHz */
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.dot = {.min = 160000, .max = 272000},
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.vco = {.min = 1809000, .max = 3564000},
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.n = {.min = 1, .max = 1},
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.m = {.min = 67, .max = 132},
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.m1 = {.min = 0, .max = 0},
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.m2 = {.min = 65, .max = 130},
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.p = {.min = 5, .max = 90},
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.p1 = {.min = 1, .max = 9},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
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.find_pll = cdv_intel_find_dp_pll,
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},
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{ /* CDV_DP_100MHz */
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.dot = {.min = 160000, .max = 272000},
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.vco = {.min = 1800000, .max = 3600000},
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.n = {.min = 2, .max = 6},
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.m = {.min = 60, .max = 164},
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.m1 = {.min = 0, .max = 0},
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.m2 = {.min = 58, .max = 162},
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.p = {.min = 5, .max = 100},
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.p1 = {.min = 1, .max = 10},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
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.find_pll = cdv_intel_find_dp_pll,
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}
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};
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#define _wait_for(COND, MS, W) ({ \
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unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
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int ret__ = 0; \
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while (!(COND)) { \
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if (time_after(jiffies, timeout__)) { \
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ret__ = -ETIMEDOUT; \
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break; \
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} \
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if (W && !in_dbg_master()) \
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msleep(W); \
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} \
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ret__; \
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})
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#define wait_for(COND, MS) _wait_for(COND, MS, 1)
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int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
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{
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int ret;
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ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
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if (ret) {
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DRM_ERROR("timeout waiting for SB to idle before read\n");
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return ret;
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}
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REG_WRITE(SB_ADDR, reg);
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REG_WRITE(SB_PCKT,
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SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
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SET_FIELD(SB_DEST_DPLL, SB_DEST) |
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SET_FIELD(0xf, SB_BYTE_ENABLE));
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ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
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if (ret) {
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DRM_ERROR("timeout waiting for SB to idle after read\n");
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return ret;
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}
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*val = REG_READ(SB_DATA);
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return 0;
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}
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int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
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{
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int ret;
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static bool dpio_debug = true;
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u32 temp;
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if (dpio_debug) {
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if (cdv_sb_read(dev, reg, &temp) == 0)
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DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
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DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
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}
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ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
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if (ret) {
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DRM_ERROR("timeout waiting for SB to idle before write\n");
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return ret;
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}
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REG_WRITE(SB_ADDR, reg);
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REG_WRITE(SB_DATA, val);
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REG_WRITE(SB_PCKT,
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SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
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SET_FIELD(SB_DEST_DPLL, SB_DEST) |
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SET_FIELD(0xf, SB_BYTE_ENABLE));
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ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
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if (ret) {
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DRM_ERROR("timeout waiting for SB to idle after write\n");
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return ret;
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}
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if (dpio_debug) {
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if (cdv_sb_read(dev, reg, &temp) == 0)
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DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
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}
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return 0;
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}
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/* Reset the DPIO configuration register. The BIOS does this at every
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* mode set.
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*/
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void cdv_sb_reset(struct drm_device *dev)
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{
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REG_WRITE(DPIO_CFG, 0);
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REG_READ(DPIO_CFG);
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REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
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}
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/* Unlike most Intel display engines, on Cedarview the DPLL registers
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* are behind this sideband bus. They must be programmed while the
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* DPLL reference clock is on in the DPLL control register, but before
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* the DPLL is enabled in the DPLL control register.
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*/
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static int
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cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
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{
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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int pipe = gma_crtc->pipe;
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u32 m, n_vco, p;
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int ret = 0;
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int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
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int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
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u32 ref_value;
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u32 lane_reg, lane_value;
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cdv_sb_reset(dev);
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REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
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udelay(100);
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/* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
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ref_value = 0x68A701;
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cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
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/* We don't know what the other fields of these regs are, so
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* leave them in place.
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*/
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/*
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* The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
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* for the pipe A/B. Display spec 1.06 has wrong definition.
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* Correct definition is like below:
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*
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* refclka mean use clock from same PLL
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*
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* if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
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*
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* if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
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*
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*/
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ret = cdv_sb_read(dev, ref_sfr, &ref_value);
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if (ret)
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return ret;
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ref_value &= ~(REF_CLK_MASK);
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/* use DPLL_A for pipeB on CRT/HDMI */
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if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
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DRM_DEBUG_KMS("use DPLLA for pipe B\n");
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ref_value |= REF_CLK_DPLLA;
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} else {
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DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
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ref_value |= REF_CLK_DPLL;
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}
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ret = cdv_sb_write(dev, ref_sfr, ref_value);
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if (ret)
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return ret;
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ret = cdv_sb_read(dev, SB_M(pipe), &m);
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if (ret)
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return ret;
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m &= ~SB_M_DIVIDER_MASK;
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m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
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ret = cdv_sb_write(dev, SB_M(pipe), m);
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if (ret)
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return ret;
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ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
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if (ret)
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return ret;
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/* Follow the BIOS to program the N_DIVIDER REG */
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n_vco &= 0xFFFF;
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n_vco |= 0x107;
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n_vco &= ~(SB_N_VCO_SEL_MASK |
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SB_N_DIVIDER_MASK |
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SB_N_CB_TUNE_MASK);
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n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
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if (clock->vco < 2250000) {
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n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
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n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
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} else if (clock->vco < 2750000) {
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n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
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n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
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} else if (clock->vco < 3300000) {
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n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
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n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
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} else {
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n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
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n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
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}
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ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
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if (ret)
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return ret;
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ret = cdv_sb_read(dev, SB_P(pipe), &p);
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if (ret)
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return ret;
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p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
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p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
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switch (clock->p2) {
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case 5:
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p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
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break;
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case 10:
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p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
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break;
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case 14:
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p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
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break;
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case 7:
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p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
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break;
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default:
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DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
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return -EINVAL;
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}
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ret = cdv_sb_write(dev, SB_P(pipe), p);
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if (ret)
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return ret;
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if (ddi_select) {
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if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
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lane_reg = PSB_LANE0;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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lane_reg = PSB_LANE1;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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} else {
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lane_reg = PSB_LANE2;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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lane_reg = PSB_LANE3;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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}
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}
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return 0;
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}
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static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
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int refclk)
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{
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const struct gma_limit_t *limit;
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if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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/*
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* Now only single-channel LVDS is supported on CDV. If it is
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* incorrect, please add the dual-channel LVDS.
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*/
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if (refclk == 96000)
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limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
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else
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limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
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} else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
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gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
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if (refclk == 27000)
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limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
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else
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limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
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} else {
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if (refclk == 27000)
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limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
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else
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limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
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}
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return limit;
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}
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/* m1 is reserved as 0 in CDV, n is a ring counter */
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static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
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{
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clock->m = clock->m2 + 2;
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clock->p = clock->p1 * clock->p2;
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clock->vco = (refclk * clock->m) / clock->n;
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clock->dot = clock->vco / clock->p;
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}
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static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
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struct drm_crtc *crtc, int target,
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int refclk,
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struct gma_clock_t *best_clock)
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{
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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struct gma_clock_t clock;
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switch (refclk) {
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case 27000:
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if (target < 200000) {
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clock.p1 = 2;
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clock.p2 = 10;
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clock.n = 1;
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clock.m1 = 0;
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clock.m2 = 118;
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} else {
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clock.p1 = 1;
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clock.p2 = 10;
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clock.n = 1;
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clock.m1 = 0;
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clock.m2 = 98;
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}
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break;
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case 100000:
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if (target < 200000) {
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clock.p1 = 2;
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clock.p2 = 10;
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clock.n = 5;
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clock.m1 = 0;
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clock.m2 = 160;
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} else {
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clock.p1 = 1;
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clock.p2 = 10;
|
|
clock.n = 5;
|
|
clock.m1 = 0;
|
|
clock.m2 = 133;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
gma_crtc->clock_funcs->clock(refclk, &clock);
|
|
memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
|
|
return true;
|
|
}
|
|
|
|
#define FIFO_PIPEA (1 << 0)
|
|
#define FIFO_PIPEB (1 << 1)
|
|
|
|
static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
|
|
{
|
|
struct drm_crtc *crtc;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct gma_crtc *gma_crtc = NULL;
|
|
|
|
crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
|
gma_crtc = to_gma_crtc(crtc);
|
|
|
|
if (crtc->primary->fb == NULL || !gma_crtc->active)
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
void cdv_disable_sr(struct drm_device *dev)
|
|
{
|
|
if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
|
|
|
|
/* Disable self-refresh before adjust WM */
|
|
REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
|
|
REG_READ(FW_BLC_SELF);
|
|
|
|
gma_wait_for_vblank(dev);
|
|
|
|
/* Cedarview workaround to write ovelay plane, which force to leave
|
|
* MAX_FIFO state.
|
|
*/
|
|
REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
|
|
REG_READ(OV_OVADD);
|
|
|
|
gma_wait_for_vblank(dev);
|
|
}
|
|
|
|
}
|
|
|
|
void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
|
|
|
|
/* Is only one pipe enabled? */
|
|
if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) {
|
|
u32 fw;
|
|
|
|
fw = REG_READ(DSPFW1);
|
|
fw &= ~DSP_FIFO_SR_WM_MASK;
|
|
fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
|
|
fw &= ~CURSOR_B_FIFO_WM_MASK;
|
|
fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
|
|
REG_WRITE(DSPFW1, fw);
|
|
|
|
fw = REG_READ(DSPFW2);
|
|
fw &= ~CURSOR_A_FIFO_WM_MASK;
|
|
fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
|
|
fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
|
|
fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
|
|
REG_WRITE(DSPFW2, fw);
|
|
|
|
REG_WRITE(DSPFW3, 0x36000000);
|
|
|
|
/* ignore FW4 */
|
|
|
|
/* Is pipe b lvds ? */
|
|
if (gma_crtc->pipe == 1 &&
|
|
gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
|
|
REG_WRITE(DSPFW5, 0x00040330);
|
|
} else {
|
|
fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
|
|
(4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
|
|
(3 << CURSOR_B_FIFO_WM1_SHIFT) |
|
|
(4 << CURSOR_FIFO_SR_WM1_SHIFT);
|
|
REG_WRITE(DSPFW5, fw);
|
|
}
|
|
|
|
REG_WRITE(DSPFW6, 0x10);
|
|
|
|
gma_wait_for_vblank(dev);
|
|
|
|
/* enable self-refresh for single pipe active */
|
|
REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
|
|
REG_READ(FW_BLC_SELF);
|
|
gma_wait_for_vblank(dev);
|
|
|
|
} else {
|
|
|
|
/* HW team suggested values... */
|
|
REG_WRITE(DSPFW1, 0x3f880808);
|
|
REG_WRITE(DSPFW2, 0x0b020202);
|
|
REG_WRITE(DSPFW3, 0x24000000);
|
|
REG_WRITE(DSPFW4, 0x08030202);
|
|
REG_WRITE(DSPFW5, 0x01010101);
|
|
REG_WRITE(DSPFW6, 0x1d0);
|
|
|
|
gma_wait_for_vblank(dev);
|
|
|
|
dev_priv->ops->disable_sr(dev);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Return the pipe currently connected to the panel fitter,
|
|
* or -1 if the panel fitter is not present or not in use
|
|
*/
|
|
static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
|
|
{
|
|
u32 pfit_control;
|
|
|
|
pfit_control = REG_READ(PFIT_CONTROL);
|
|
|
|
/* See if the panel fitter is in use */
|
|
if ((pfit_control & PFIT_ENABLE) == 0)
|
|
return -1;
|
|
return (pfit_control >> 29) & 0x3;
|
|
}
|
|
|
|
static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode,
|
|
int x, int y,
|
|
struct drm_framebuffer *old_fb)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
|
|
int pipe = gma_crtc->pipe;
|
|
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
|
int refclk;
|
|
struct gma_clock_t clock;
|
|
u32 dpll = 0, dspcntr, pipeconf;
|
|
bool ok;
|
|
bool is_crt = false, is_lvds = false, is_tv = false;
|
|
bool is_hdmi = false, is_dp = false;
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
|
struct drm_connector *connector;
|
|
const struct gma_limit_t *limit;
|
|
u32 ddi_select = 0;
|
|
bool is_edp = false;
|
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
struct gma_encoder *gma_encoder =
|
|
gma_attached_encoder(connector);
|
|
|
|
if (!connector->encoder
|
|
|| connector->encoder->crtc != crtc)
|
|
continue;
|
|
|
|
ddi_select = gma_encoder->ddi_select;
|
|
switch (gma_encoder->type) {
|
|
case INTEL_OUTPUT_LVDS:
|
|
is_lvds = true;
|
|
break;
|
|
case INTEL_OUTPUT_TVOUT:
|
|
is_tv = true;
|
|
break;
|
|
case INTEL_OUTPUT_ANALOG:
|
|
is_crt = true;
|
|
break;
|
|
case INTEL_OUTPUT_HDMI:
|
|
is_hdmi = true;
|
|
break;
|
|
case INTEL_OUTPUT_DISPLAYPORT:
|
|
is_dp = true;
|
|
break;
|
|
case INTEL_OUTPUT_EDP:
|
|
is_edp = true;
|
|
break;
|
|
default:
|
|
DRM_ERROR("invalid output type.\n");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
if (dev_priv->dplla_96mhz)
|
|
/* low-end sku, 96/100 mhz */
|
|
refclk = 96000;
|
|
else
|
|
/* high-end sku, 27/100 mhz */
|
|
refclk = 27000;
|
|
if (is_dp || is_edp) {
|
|
/*
|
|
* Based on the spec the low-end SKU has only CRT/LVDS. So it is
|
|
* unnecessary to consider it for DP/eDP.
|
|
* On the high-end SKU, it will use the 27/100M reference clk
|
|
* for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
|
|
* it will be 27MHz. From the VBIOS code it seems that the pipe A choose
|
|
* 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
|
|
*/
|
|
if (pipe == 0)
|
|
refclk = 27000;
|
|
else
|
|
refclk = 100000;
|
|
}
|
|
|
|
if (is_lvds && dev_priv->lvds_use_ssc) {
|
|
refclk = dev_priv->lvds_ssc_freq * 1000;
|
|
DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
|
|
}
|
|
|
|
drm_mode_debug_printmodeline(adjusted_mode);
|
|
|
|
limit = gma_crtc->clock_funcs->limit(crtc, refclk);
|
|
|
|
ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
|
|
&clock);
|
|
if (!ok) {
|
|
DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
|
|
adjusted_mode->clock, clock.dot);
|
|
return 0;
|
|
}
|
|
|
|
dpll = DPLL_VGA_MODE_DIS;
|
|
if (is_tv) {
|
|
/* XXX: just matching BIOS for now */
|
|
/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
|
|
dpll |= 3;
|
|
}
|
|
/* dpll |= PLL_REF_INPUT_DREFCLK; */
|
|
|
|
if (is_dp || is_edp) {
|
|
cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
|
|
} else {
|
|
REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
|
|
REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
|
|
REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
|
|
REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
|
|
}
|
|
|
|
dpll |= DPLL_SYNCLOCK_ENABLE;
|
|
/* if (is_lvds)
|
|
dpll |= DPLLB_MODE_LVDS;
|
|
else
|
|
dpll |= DPLLB_MODE_DAC_SERIAL; */
|
|
/* dpll |= (2 << 11); */
|
|
|
|
/* setup pipeconf */
|
|
pipeconf = REG_READ(map->conf);
|
|
|
|
pipeconf &= ~(PIPE_BPC_MASK);
|
|
if (is_edp) {
|
|
switch (dev_priv->edp.bpp) {
|
|
case 24:
|
|
pipeconf |= PIPE_8BPC;
|
|
break;
|
|
case 18:
|
|
pipeconf |= PIPE_6BPC;
|
|
break;
|
|
case 30:
|
|
pipeconf |= PIPE_10BPC;
|
|
break;
|
|
default:
|
|
pipeconf |= PIPE_8BPC;
|
|
break;
|
|
}
|
|
} else if (is_lvds) {
|
|
/* the BPC will be 6 if it is 18-bit LVDS panel */
|
|
if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
|
|
pipeconf |= PIPE_8BPC;
|
|
else
|
|
pipeconf |= PIPE_6BPC;
|
|
} else
|
|
pipeconf |= PIPE_8BPC;
|
|
|
|
/* Set up the display plane register */
|
|
dspcntr = DISPPLANE_GAMMA_ENABLE;
|
|
|
|
if (pipe == 0)
|
|
dspcntr |= DISPPLANE_SEL_PIPE_A;
|
|
else
|
|
dspcntr |= DISPPLANE_SEL_PIPE_B;
|
|
|
|
dspcntr |= DISPLAY_PLANE_ENABLE;
|
|
pipeconf |= PIPEACONF_ENABLE;
|
|
|
|
REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
|
|
REG_READ(map->dpll);
|
|
|
|
cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
|
|
|
|
udelay(150);
|
|
|
|
|
|
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
|
|
* This is an exception to the general rule that mode_set doesn't turn
|
|
* things on.
|
|
*/
|
|
if (is_lvds) {
|
|
u32 lvds = REG_READ(LVDS);
|
|
|
|
lvds |=
|
|
LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
|
|
LVDS_PIPEB_SELECT;
|
|
/* Set the B0-B3 data pairs corresponding to
|
|
* whether we're going to
|
|
* set the DPLLs for dual-channel mode or not.
|
|
*/
|
|
if (clock.p2 == 7)
|
|
lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
|
|
else
|
|
lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
|
|
|
|
/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
|
|
* appropriately here, but we need to look more
|
|
* thoroughly into how panels behave in the two modes.
|
|
*/
|
|
|
|
REG_WRITE(LVDS, lvds);
|
|
REG_READ(LVDS);
|
|
}
|
|
|
|
dpll |= DPLL_VCO_ENABLE;
|
|
|
|
/* Disable the panel fitter if it was on our pipe */
|
|
if (cdv_intel_panel_fitter_pipe(dev) == pipe)
|
|
REG_WRITE(PFIT_CONTROL, 0);
|
|
|
|
DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
|
|
drm_mode_debug_printmodeline(mode);
|
|
|
|
REG_WRITE(map->dpll,
|
|
(REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
|
|
REG_READ(map->dpll);
|
|
/* Wait for the clocks to stabilize. */
|
|
udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
|
|
|
|
if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
|
|
dev_err(dev->dev, "Failed to get DPLL lock\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
{
|
|
int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
|
|
REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
|
|
}
|
|
|
|
REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
|
|
((adjusted_mode->crtc_htotal - 1) << 16));
|
|
REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
|
|
((adjusted_mode->crtc_hblank_end - 1) << 16));
|
|
REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
|
|
((adjusted_mode->crtc_hsync_end - 1) << 16));
|
|
REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
|
|
((adjusted_mode->crtc_vtotal - 1) << 16));
|
|
REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
|
|
((adjusted_mode->crtc_vblank_end - 1) << 16));
|
|
REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
|
|
((adjusted_mode->crtc_vsync_end - 1) << 16));
|
|
/* pipesrc and dspsize control the size that is scaled from,
|
|
* which should always be the user's requested size.
|
|
*/
|
|
REG_WRITE(map->size,
|
|
((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
|
|
REG_WRITE(map->pos, 0);
|
|
REG_WRITE(map->src,
|
|
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
|
|
REG_WRITE(map->conf, pipeconf);
|
|
REG_READ(map->conf);
|
|
|
|
gma_wait_for_vblank(dev);
|
|
|
|
REG_WRITE(map->cntr, dspcntr);
|
|
|
|
/* Flush the plane changes */
|
|
{
|
|
const struct drm_crtc_helper_funcs *crtc_funcs =
|
|
crtc->helper_private;
|
|
crtc_funcs->mode_set_base(crtc, x, y, old_fb);
|
|
}
|
|
|
|
gma_wait_for_vblank(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
|
|
|
|
/* FIXME: why are we using this, should it be cdv_ in this tree ? */
|
|
|
|
static void i8xx_clock(int refclk, struct gma_clock_t *clock)
|
|
{
|
|
clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
|
|
clock->p = clock->p1 * clock->p2;
|
|
clock->vco = refclk * clock->m / (clock->n + 2);
|
|
clock->dot = clock->vco / clock->p;
|
|
}
|
|
|
|
/* Returns the clock of the currently programmed mode of the given pipe. */
|
|
static int cdv_intel_crtc_clock_get(struct drm_device *dev,
|
|
struct drm_crtc *crtc)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
|
|
int pipe = gma_crtc->pipe;
|
|
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
|
u32 dpll;
|
|
u32 fp;
|
|
struct gma_clock_t clock;
|
|
bool is_lvds;
|
|
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
|
|
|
|
if (gma_power_begin(dev, false)) {
|
|
dpll = REG_READ(map->dpll);
|
|
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
|
|
fp = REG_READ(map->fp0);
|
|
else
|
|
fp = REG_READ(map->fp1);
|
|
is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
|
|
gma_power_end(dev);
|
|
} else {
|
|
dpll = p->dpll;
|
|
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
|
|
fp = p->fp0;
|
|
else
|
|
fp = p->fp1;
|
|
|
|
is_lvds = (pipe == 1) &&
|
|
(dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
|
|
}
|
|
|
|
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
|
|
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
|
|
clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
|
|
|
|
if (is_lvds) {
|
|
clock.p1 =
|
|
ffs((dpll &
|
|
DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
|
|
DPLL_FPA01_P1_POST_DIV_SHIFT);
|
|
if (clock.p1 == 0) {
|
|
clock.p1 = 4;
|
|
dev_err(dev->dev, "PLL %d\n", dpll);
|
|
}
|
|
clock.p2 = 14;
|
|
|
|
if ((dpll & PLL_REF_INPUT_MASK) ==
|
|
PLLB_REF_INPUT_SPREADSPECTRUMIN) {
|
|
/* XXX: might not be 66MHz */
|
|
i8xx_clock(66000, &clock);
|
|
} else
|
|
i8xx_clock(48000, &clock);
|
|
} else {
|
|
if (dpll & PLL_P1_DIVIDE_BY_TWO)
|
|
clock.p1 = 2;
|
|
else {
|
|
clock.p1 =
|
|
((dpll &
|
|
DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
|
|
DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
|
|
}
|
|
if (dpll & PLL_P2_DIVIDE_BY_4)
|
|
clock.p2 = 4;
|
|
else
|
|
clock.p2 = 2;
|
|
|
|
i8xx_clock(48000, &clock);
|
|
}
|
|
|
|
/* XXX: It would be nice to validate the clocks, but we can't reuse
|
|
* i830PllIsValid() because it relies on the xf86_config connector
|
|
* configuration being accurate, which it isn't necessarily.
|
|
*/
|
|
|
|
return clock.dot;
|
|
}
|
|
|
|
/** Returns the currently programmed mode of the given pipe. */
|
|
struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
|
|
struct drm_crtc *crtc)
|
|
{
|
|
struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
|
|
int pipe = gma_crtc->pipe;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
|
|
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
|
struct drm_display_mode *mode;
|
|
int htot;
|
|
int hsync;
|
|
int vtot;
|
|
int vsync;
|
|
|
|
if (gma_power_begin(dev, false)) {
|
|
htot = REG_READ(map->htotal);
|
|
hsync = REG_READ(map->hsync);
|
|
vtot = REG_READ(map->vtotal);
|
|
vsync = REG_READ(map->vsync);
|
|
gma_power_end(dev);
|
|
} else {
|
|
htot = p->htotal;
|
|
hsync = p->hsync;
|
|
vtot = p->vtotal;
|
|
vsync = p->vsync;
|
|
}
|
|
|
|
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
|
|
if (!mode)
|
|
return NULL;
|
|
|
|
mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
|
|
mode->hdisplay = (htot & 0xffff) + 1;
|
|
mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
|
|
mode->hsync_start = (hsync & 0xffff) + 1;
|
|
mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
|
|
mode->vdisplay = (vtot & 0xffff) + 1;
|
|
mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
|
|
mode->vsync_start = (vsync & 0xffff) + 1;
|
|
mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
|
|
|
|
drm_mode_set_name(mode);
|
|
drm_mode_set_crtcinfo(mode, 0);
|
|
|
|
return mode;
|
|
}
|
|
|
|
const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
|
|
.dpms = gma_crtc_dpms,
|
|
.mode_set = cdv_intel_crtc_mode_set,
|
|
.mode_set_base = gma_pipe_set_base,
|
|
.prepare = gma_crtc_prepare,
|
|
.commit = gma_crtc_commit,
|
|
.disable = gma_crtc_disable,
|
|
};
|
|
|
|
const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
|
|
.cursor_set = gma_crtc_cursor_set,
|
|
.cursor_move = gma_crtc_cursor_move,
|
|
.gamma_set = gma_crtc_gamma_set,
|
|
.set_config = gma_crtc_set_config,
|
|
.destroy = gma_crtc_destroy,
|
|
};
|
|
|
|
const struct gma_clock_funcs cdv_clock_funcs = {
|
|
.clock = cdv_intel_clock,
|
|
.limit = cdv_intel_limit,
|
|
.pll_is_valid = gma_pll_is_valid,
|
|
};
|