![Chris Wilson](/assets/img/avatar_default.png)
Some pieces of code are independent of hardware but are very tricky to exercise through the normal userspace ABI or via debugfs hooks. Being able to create mock unit tests and execute them through CI is vital. Start by adding a central point where we can execute unit tests and a parameter to enable them. This is disabled by default as the expectation is that these tests will occasionally explode. To facilitate integration with igt, any parameter beginning with i915.igt__ is interpreted as a subtest executable independently via igt/drv_selftest. Two classes of selftests are recognised: mock unit tests and integration tests. Mock unit tests are run as soon as the module is loaded, before the device is probed. At that point there is no driver instantiated and all hw interactions must be "mocked". This is very useful for writing universal tests to exercise code not typically run on a broad range of architectures. Alternatively, you can hook into the live selftests and run when the device has been instantiated - hw interactions are real. v2: Add a macro for compiling conditional code for mock objects inside real objects. v3: Differentiate between mock unit tests and late integration test. v4: List the tests in natural order, use igt to sort after modparam. v5: s/late/live/ v6: s/unsigned long/unsigned int/ v7: Use igt_ prefixes for long helpers. v8: Deobfuscate macros overriding functions, stop using -I$(src) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170213171558.20942-1-chris@chris-wilson.co.uk
580 lines
15 KiB
C
580 lines
15 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/console.h>
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#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include "i915_drv.h"
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#include "i915_selftest.h"
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#define GEN_DEFAULT_PIPEOFFSETS \
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.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
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PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
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.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
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TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
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.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
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#define GEN_CHV_PIPEOFFSETS \
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.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
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CHV_PIPE_C_OFFSET }, \
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.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
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CHV_TRANSCODER_C_OFFSET, }, \
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.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
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CHV_PALETTE_C_OFFSET }
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#define CURSOR_OFFSETS \
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.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
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#define IVB_CURSOR_OFFSETS \
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.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
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#define BDW_COLORS \
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.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
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#define CHV_COLORS \
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.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
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/* Keep in gen based order, and chronological order within a gen */
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#define GEN2_FEATURES \
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.gen = 2, .num_pipes = 1, \
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.has_overlay = 1, .overlay_needs_physical = 1, \
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.has_gmch_display = 1, \
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.hws_needs_physical = 1, \
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.ring_mask = RENDER_RING, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_i830_info = {
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GEN2_FEATURES,
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.platform = INTEL_I830,
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.is_mobile = 1, .cursor_needs_physical = 1,
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.num_pipes = 2, /* legal, last one wins */
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};
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static const struct intel_device_info intel_i845g_info = {
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GEN2_FEATURES,
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.platform = INTEL_I845G,
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};
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static const struct intel_device_info intel_i85x_info = {
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GEN2_FEATURES,
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.platform = INTEL_I85X, .is_mobile = 1,
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.num_pipes = 2, /* legal, last one wins */
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.cursor_needs_physical = 1,
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.has_fbc = 1,
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};
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static const struct intel_device_info intel_i865g_info = {
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GEN2_FEATURES,
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.platform = INTEL_I865G,
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};
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#define GEN3_FEATURES \
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.gen = 3, .num_pipes = 2, \
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.has_gmch_display = 1, \
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.ring_mask = RENDER_RING, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_i915g_info = {
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GEN3_FEATURES,
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.platform = INTEL_I915G, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_i915gm_info = {
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GEN3_FEATURES,
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.platform = INTEL_I915GM,
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.is_mobile = 1,
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.cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.supports_tv = 1,
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.has_fbc = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_i945g_info = {
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GEN3_FEATURES,
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.platform = INTEL_I945G,
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.has_hotplug = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_i945gm_info = {
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GEN3_FEATURES,
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.platform = INTEL_I945GM, .is_mobile = 1,
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.has_hotplug = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.supports_tv = 1,
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.has_fbc = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_g33_info = {
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GEN3_FEATURES,
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.platform = INTEL_G33,
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.has_hotplug = 1,
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.has_overlay = 1,
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};
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static const struct intel_device_info intel_pineview_info = {
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GEN3_FEATURES,
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.platform = INTEL_PINEVIEW, .is_mobile = 1,
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.has_hotplug = 1,
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.has_overlay = 1,
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};
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#define GEN4_FEATURES \
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.gen = 4, .num_pipes = 2, \
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.has_hotplug = 1, \
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.has_gmch_display = 1, \
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.ring_mask = RENDER_RING, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_i965g_info = {
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GEN4_FEATURES,
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.platform = INTEL_I965G,
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.has_overlay = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_i965gm_info = {
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GEN4_FEATURES,
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.platform = INTEL_I965GM,
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.is_mobile = 1, .has_fbc = 1,
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.has_overlay = 1,
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.supports_tv = 1,
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.hws_needs_physical = 1,
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};
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static const struct intel_device_info intel_g45_info = {
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GEN4_FEATURES,
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.platform = INTEL_G45,
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.has_pipe_cxsr = 1,
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.ring_mask = RENDER_RING | BSD_RING,
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};
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static const struct intel_device_info intel_gm45_info = {
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GEN4_FEATURES,
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.platform = INTEL_GM45,
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.is_mobile = 1, .has_fbc = 1,
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.has_pipe_cxsr = 1,
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.supports_tv = 1,
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.ring_mask = RENDER_RING | BSD_RING,
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};
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#define GEN5_FEATURES \
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.gen = 5, .num_pipes = 2, \
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.has_hotplug = 1, \
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.has_gmbus_irq = 1, \
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.ring_mask = RENDER_RING | BSD_RING, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_ironlake_d_info = {
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GEN5_FEATURES,
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.platform = INTEL_IRONLAKE,
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};
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static const struct intel_device_info intel_ironlake_m_info = {
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GEN5_FEATURES,
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.platform = INTEL_IRONLAKE,
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.is_mobile = 1,
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};
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#define GEN6_FEATURES \
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.gen = 6, .num_pipes = 2, \
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.has_hotplug = 1, \
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.has_fbc = 1, \
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
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.has_llc = 1, \
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.has_rc6 = 1, \
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.has_rc6p = 1, \
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.has_gmbus_irq = 1, \
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.has_hw_contexts = 1, \
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.has_aliasing_ppgtt = 1, \
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GEN_DEFAULT_PIPEOFFSETS, \
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CURSOR_OFFSETS
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static const struct intel_device_info intel_sandybridge_d_info = {
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GEN6_FEATURES,
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.platform = INTEL_SANDYBRIDGE,
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};
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static const struct intel_device_info intel_sandybridge_m_info = {
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GEN6_FEATURES,
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.platform = INTEL_SANDYBRIDGE,
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.is_mobile = 1,
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};
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#define GEN7_FEATURES \
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.gen = 7, .num_pipes = 3, \
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.has_hotplug = 1, \
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.has_fbc = 1, \
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
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.has_llc = 1, \
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.has_rc6 = 1, \
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.has_rc6p = 1, \
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.has_gmbus_irq = 1, \
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.has_hw_contexts = 1, \
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.has_aliasing_ppgtt = 1, \
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.has_full_ppgtt = 1, \
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GEN_DEFAULT_PIPEOFFSETS, \
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IVB_CURSOR_OFFSETS
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static const struct intel_device_info intel_ivybridge_d_info = {
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GEN7_FEATURES,
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.platform = INTEL_IVYBRIDGE,
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.has_l3_dpf = 1,
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};
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static const struct intel_device_info intel_ivybridge_m_info = {
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GEN7_FEATURES,
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.platform = INTEL_IVYBRIDGE,
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.is_mobile = 1,
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.has_l3_dpf = 1,
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};
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static const struct intel_device_info intel_ivybridge_q_info = {
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GEN7_FEATURES,
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.platform = INTEL_IVYBRIDGE,
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.num_pipes = 0, /* legal, last one wins */
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.has_l3_dpf = 1,
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};
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static const struct intel_device_info intel_valleyview_info = {
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.platform = INTEL_VALLEYVIEW,
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.gen = 7,
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.is_lp = 1,
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.num_pipes = 2,
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.has_psr = 1,
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.has_runtime_pm = 1,
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.has_rc6 = 1,
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.has_gmbus_irq = 1,
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.has_hw_contexts = 1,
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.has_gmch_display = 1,
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.has_hotplug = 1,
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.has_aliasing_ppgtt = 1,
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.has_full_ppgtt = 1,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
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.display_mmio_offset = VLV_DISPLAY_BASE,
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GEN_DEFAULT_PIPEOFFSETS,
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CURSOR_OFFSETS
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};
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#define HSW_FEATURES \
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GEN7_FEATURES, \
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
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.has_ddi = 1, \
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.has_fpga_dbg = 1, \
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.has_psr = 1, \
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.has_resource_streamer = 1, \
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.has_dp_mst = 1, \
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.has_rc6p = 0 /* RC6p removed-by HSW */, \
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.has_runtime_pm = 1
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static const struct intel_device_info intel_haswell_info = {
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HSW_FEATURES,
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.platform = INTEL_HASWELL,
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.has_l3_dpf = 1,
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};
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#define BDW_FEATURES \
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HSW_FEATURES, \
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BDW_COLORS, \
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.has_logical_ring_contexts = 1, \
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.has_full_48bit_ppgtt = 1, \
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.has_64bit_reloc = 1
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static const struct intel_device_info intel_broadwell_info = {
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BDW_FEATURES,
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.gen = 8,
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.platform = INTEL_BROADWELL,
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};
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static const struct intel_device_info intel_broadwell_gt3_info = {
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BDW_FEATURES,
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.gen = 8,
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.platform = INTEL_BROADWELL,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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};
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static const struct intel_device_info intel_cherryview_info = {
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.gen = 8, .num_pipes = 3,
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.has_hotplug = 1,
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.is_lp = 1,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
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.platform = INTEL_CHERRYVIEW,
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.has_64bit_reloc = 1,
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.has_psr = 1,
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.has_runtime_pm = 1,
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.has_resource_streamer = 1,
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.has_rc6 = 1,
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.has_gmbus_irq = 1,
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.has_hw_contexts = 1,
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.has_logical_ring_contexts = 1,
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.has_gmch_display = 1,
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.has_aliasing_ppgtt = 1,
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.has_full_ppgtt = 1,
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.display_mmio_offset = VLV_DISPLAY_BASE,
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GEN_CHV_PIPEOFFSETS,
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CURSOR_OFFSETS,
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CHV_COLORS,
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};
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static const struct intel_device_info intel_skylake_info = {
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BDW_FEATURES,
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.platform = INTEL_SKYLAKE,
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.gen = 9,
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.has_csr = 1,
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.has_guc = 1,
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.ddb_size = 896,
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};
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static const struct intel_device_info intel_skylake_gt3_info = {
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BDW_FEATURES,
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.platform = INTEL_SKYLAKE,
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.gen = 9,
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.has_csr = 1,
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.has_guc = 1,
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.ddb_size = 896,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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};
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#define GEN9_LP_FEATURES \
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.gen = 9, \
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.is_lp = 1, \
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.has_hotplug = 1, \
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
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.num_pipes = 3, \
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.has_64bit_reloc = 1, \
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.has_ddi = 1, \
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.has_fpga_dbg = 1, \
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.has_fbc = 1, \
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.has_runtime_pm = 1, \
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.has_pooled_eu = 0, \
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.has_csr = 1, \
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.has_resource_streamer = 1, \
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.has_rc6 = 1, \
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.has_dp_mst = 1, \
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.has_gmbus_irq = 1, \
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.has_hw_contexts = 1, \
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.has_logical_ring_contexts = 1, \
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.has_guc = 1, \
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.has_decoupled_mmio = 1, \
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.has_aliasing_ppgtt = 1, \
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.has_full_ppgtt = 1, \
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.has_full_48bit_ppgtt = 1, \
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GEN_DEFAULT_PIPEOFFSETS, \
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IVB_CURSOR_OFFSETS, \
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BDW_COLORS
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static const struct intel_device_info intel_broxton_info = {
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GEN9_LP_FEATURES,
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.platform = INTEL_BROXTON,
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.ddb_size = 512,
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};
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static const struct intel_device_info intel_geminilake_info = {
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GEN9_LP_FEATURES,
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.platform = INTEL_GEMINILAKE,
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.is_alpha_support = 1,
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.ddb_size = 1024,
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.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
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};
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static const struct intel_device_info intel_kabylake_info = {
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BDW_FEATURES,
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.platform = INTEL_KABYLAKE,
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.gen = 9,
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.has_csr = 1,
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.has_guc = 1,
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.ddb_size = 896,
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};
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static const struct intel_device_info intel_kabylake_gt3_info = {
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BDW_FEATURES,
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.platform = INTEL_KABYLAKE,
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.gen = 9,
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.has_csr = 1,
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.has_guc = 1,
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.ddb_size = 896,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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};
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/*
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* Make sure any device matches here are from most specific to most
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* general. For example, since the Quanta match is based on the subsystem
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* and subvendor IDs, we need it to come before the more general IVB
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* PCI ID matches, otherwise we'll use the wrong info struct above.
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*/
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static const struct pci_device_id pciidlist[] = {
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INTEL_I830_IDS(&intel_i830_info),
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INTEL_I845G_IDS(&intel_i845g_info),
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INTEL_I85X_IDS(&intel_i85x_info),
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INTEL_I865G_IDS(&intel_i865g_info),
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INTEL_I915G_IDS(&intel_i915g_info),
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INTEL_I915GM_IDS(&intel_i915gm_info),
|
|
INTEL_I945G_IDS(&intel_i945g_info),
|
|
INTEL_I945GM_IDS(&intel_i945gm_info),
|
|
INTEL_I965G_IDS(&intel_i965g_info),
|
|
INTEL_G33_IDS(&intel_g33_info),
|
|
INTEL_I965GM_IDS(&intel_i965gm_info),
|
|
INTEL_GM45_IDS(&intel_gm45_info),
|
|
INTEL_G45_IDS(&intel_g45_info),
|
|
INTEL_PINEVIEW_IDS(&intel_pineview_info),
|
|
INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
|
|
INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
|
|
INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
|
|
INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
|
|
INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
|
|
INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
|
|
INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
|
|
INTEL_HSW_IDS(&intel_haswell_info),
|
|
INTEL_VLV_IDS(&intel_valleyview_info),
|
|
INTEL_BDW_GT12_IDS(&intel_broadwell_info),
|
|
INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
|
|
INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
|
|
INTEL_CHV_IDS(&intel_cherryview_info),
|
|
INTEL_SKL_GT1_IDS(&intel_skylake_info),
|
|
INTEL_SKL_GT2_IDS(&intel_skylake_info),
|
|
INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
|
|
INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
|
|
INTEL_BXT_IDS(&intel_broxton_info),
|
|
INTEL_GLK_IDS(&intel_geminilake_info),
|
|
INTEL_KBL_GT1_IDS(&intel_kabylake_info),
|
|
INTEL_KBL_GT2_IDS(&intel_kabylake_info),
|
|
INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
|
|
INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
|
|
{0, 0, 0}
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, pciidlist);
|
|
|
|
static void i915_pci_remove(struct pci_dev *pdev)
|
|
{
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
i915_driver_unload(dev);
|
|
drm_dev_unref(dev);
|
|
}
|
|
|
|
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
struct intel_device_info *intel_info =
|
|
(struct intel_device_info *) ent->driver_data;
|
|
int err;
|
|
|
|
if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
|
|
DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
|
|
"See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
|
|
"to enable support in this kernel version, or check for kernel updates.\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Only bind to function 0 of the device. Early generations
|
|
* used function 1 as a placeholder for multi-head. This causes
|
|
* us confusion instead, especially on the systems where both
|
|
* functions have the same PCI-ID!
|
|
*/
|
|
if (PCI_FUNC(pdev->devfn))
|
|
return -ENODEV;
|
|
|
|
/*
|
|
* apple-gmux is needed on dual GPU MacBook Pro
|
|
* to probe the panel if we're the inactive GPU.
|
|
*/
|
|
if (vga_switcheroo_client_probe_defer(pdev))
|
|
return -EPROBE_DEFER;
|
|
|
|
err = i915_driver_load(pdev, ent);
|
|
if (err)
|
|
return err;
|
|
|
|
err = i915_live_selftests(pdev);
|
|
if (err) {
|
|
i915_pci_remove(pdev);
|
|
return err > 0 ? -ENOTTY : err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct pci_driver i915_pci_driver = {
|
|
.name = DRIVER_NAME,
|
|
.id_table = pciidlist,
|
|
.probe = i915_pci_probe,
|
|
.remove = i915_pci_remove,
|
|
.driver.pm = &i915_pm_ops,
|
|
};
|
|
|
|
static int __init i915_init(void)
|
|
{
|
|
bool use_kms = true;
|
|
int err;
|
|
|
|
err = i915_mock_selftests();
|
|
if (err)
|
|
return err > 0 ? 0 : err;
|
|
|
|
/*
|
|
* Enable KMS by default, unless explicitly overriden by
|
|
* either the i915.modeset prarameter or by the
|
|
* vga_text_mode_force boot option.
|
|
*/
|
|
|
|
if (i915.modeset == 0)
|
|
use_kms = false;
|
|
|
|
if (vgacon_text_force() && i915.modeset == -1)
|
|
use_kms = false;
|
|
|
|
if (!use_kms) {
|
|
/* Silently fail loading to not upset userspace. */
|
|
DRM_DEBUG_DRIVER("KMS disabled.\n");
|
|
return 0;
|
|
}
|
|
|
|
return pci_register_driver(&i915_pci_driver);
|
|
}
|
|
|
|
static void __exit i915_exit(void)
|
|
{
|
|
if (!i915_pci_driver.driver.owner)
|
|
return;
|
|
|
|
pci_unregister_driver(&i915_pci_driver);
|
|
}
|
|
|
|
module_init(i915_init);
|
|
module_exit(i915_exit);
|
|
|
|
MODULE_AUTHOR("Tungsten Graphics, Inc.");
|
|
MODULE_AUTHOR("Intel Corporation");
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL and additional rights");
|