![Jani Nikula](/assets/img/avatar_default.png)
Emphasize that the VBT file is nowadays more about initializing and running stuff based on the VBT contents, not so much about being a "panel driver". No functional changes. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Bob Paauwe <bob.j.paauwe@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/b13cb012a555ff5eb56b5e4bb2b0205c3e025a99.1488810382.git.jani.nikula@intel.com
799 lines
23 KiB
C
799 lines
23 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Author: Shobhit Kumar <shobhit.kumar@intel.com>
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*
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*/
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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#include <drm/i915_drm.h>
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#include <linux/gpio/consumer.h>
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#include <linux/slab.h>
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#include <video/mipi_display.h>
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#include <asm/intel-mid.h>
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#include <video/mipi_display.h>
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#include "i915_drv.h"
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#include "intel_drv.h"
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#include "intel_dsi.h"
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#define MIPI_TRANSFER_MODE_SHIFT 0
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#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
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#define MIPI_PORT_SHIFT 3
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#define PREPARE_CNT_MAX 0x3F
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#define EXIT_ZERO_CNT_MAX 0x3F
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#define CLK_ZERO_CNT_MAX 0xFF
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#define TRAIL_CNT_MAX 0x1F
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#define NS_KHZ_RATIO 1000000
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/* base offsets for gpio pads */
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#define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
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#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
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#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
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#define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
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#define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
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#define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
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#define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
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#define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
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#define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
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#define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
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#define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
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#define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
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#define VLV_GPIO_PCONF0(base_offset) (base_offset)
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#define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
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struct gpio_map {
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u16 base_offset;
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bool init;
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};
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static struct gpio_map vlv_gpio_table[] = {
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{ VLV_GPIO_NC_0_HV_DDI0_HPD },
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{ VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
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{ VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
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{ VLV_GPIO_NC_3_PANEL0_VDDEN },
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{ VLV_GPIO_NC_4_PANEL0_BKLTEN },
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{ VLV_GPIO_NC_5_PANEL0_BKLTCTL },
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{ VLV_GPIO_NC_6_HV_DDI1_HPD },
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{ VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
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{ VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
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{ VLV_GPIO_NC_9_PANEL1_VDDEN },
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{ VLV_GPIO_NC_10_PANEL1_BKLTEN },
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{ VLV_GPIO_NC_11_PANEL1_BKLTCTL },
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};
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#define CHV_GPIO_IDX_START_N 0
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#define CHV_GPIO_IDX_START_E 73
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#define CHV_GPIO_IDX_START_SW 100
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#define CHV_GPIO_IDX_START_SE 198
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#define CHV_VBT_MAX_PINS_PER_FMLY 15
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#define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
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#define CHV_GPIO_GPIOEN (1 << 15)
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#define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
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#define CHV_GPIO_GPIOCFG_GPO (1 << 8)
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#define CHV_GPIO_GPIOCFG_GPI (2 << 8)
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#define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
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#define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
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#define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
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#define CHV_GPIO_CFGLOCK (1 << 31)
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static inline enum port intel_dsi_seq_port_to_port(u8 port)
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{
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return port ? PORT_C : PORT_A;
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}
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static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
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const u8 *data)
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{
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struct mipi_dsi_device *dsi_device;
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u8 type, flags, seq_port;
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u16 len;
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enum port port;
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DRM_DEBUG_KMS("\n");
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flags = *data++;
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type = *data++;
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len = *((u16 *) data);
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data += 2;
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seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
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/* For DSI single link on Port A & C, the seq_port value which is
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* parsed from Sequence Block#53 of VBT has been set to 0
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* Now, read/write of packets for the DSI single link on Port A and
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* Port C will based on the DVO port from VBT block 2.
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*/
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if (intel_dsi->ports == (1 << PORT_C))
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port = PORT_C;
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else
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port = intel_dsi_seq_port_to_port(seq_port);
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dsi_device = intel_dsi->dsi_hosts[port]->device;
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if (!dsi_device) {
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DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
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goto out;
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}
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if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
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dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
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else
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dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
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dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
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switch (type) {
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case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
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mipi_dsi_generic_write(dsi_device, NULL, 0);
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
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mipi_dsi_generic_write(dsi_device, data, 1);
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
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mipi_dsi_generic_write(dsi_device, data, 2);
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break;
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case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
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DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
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break;
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case MIPI_DSI_GENERIC_LONG_WRITE:
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mipi_dsi_generic_write(dsi_device, data, len);
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break;
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case MIPI_DSI_DCS_SHORT_WRITE:
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mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
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break;
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
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break;
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case MIPI_DSI_DCS_READ:
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DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
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break;
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case MIPI_DSI_DCS_LONG_WRITE:
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mipi_dsi_dcs_write_buffer(dsi_device, data, len);
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break;
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}
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wait_for_dsi_fifo_empty(intel_dsi, port);
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out:
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data += len;
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return data;
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}
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static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
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{
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u32 delay = *((const u32 *) data);
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DRM_DEBUG_KMS("\n");
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usleep_range(delay, delay + 10);
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data += 4;
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return data;
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}
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static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
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u8 gpio_source, u8 gpio_index, bool value)
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{
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struct gpio_map *map;
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u16 pconf0, padval;
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u32 tmp;
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u8 port;
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if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
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DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
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return;
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}
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map = &vlv_gpio_table[gpio_index];
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if (dev_priv->vbt.dsi.seq_version >= 3) {
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/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
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port = IOSF_PORT_GPIO_NC;
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} else {
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if (gpio_source == 0) {
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port = IOSF_PORT_GPIO_NC;
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} else if (gpio_source == 1) {
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DRM_DEBUG_KMS("SC gpio not supported\n");
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return;
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} else {
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DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
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return;
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}
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}
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pconf0 = VLV_GPIO_PCONF0(map->base_offset);
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padval = VLV_GPIO_PAD_VAL(map->base_offset);
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mutex_lock(&dev_priv->sb_lock);
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if (!map->init) {
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/* FIXME: remove constant below */
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vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
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map->init = true;
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}
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tmp = 0x4 | value;
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vlv_iosf_sb_write(dev_priv, port, padval, tmp);
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mutex_unlock(&dev_priv->sb_lock);
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}
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static void chv_exec_gpio(struct drm_i915_private *dev_priv,
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u8 gpio_source, u8 gpio_index, bool value)
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{
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u16 cfg0, cfg1;
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u16 family_num;
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u8 port;
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if (dev_priv->vbt.dsi.seq_version >= 3) {
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if (gpio_index >= CHV_GPIO_IDX_START_SE) {
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/* XXX: it's unclear whether 255->57 is part of SE. */
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gpio_index -= CHV_GPIO_IDX_START_SE;
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port = CHV_IOSF_PORT_GPIO_SE;
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} else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
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gpio_index -= CHV_GPIO_IDX_START_SW;
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port = CHV_IOSF_PORT_GPIO_SW;
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} else if (gpio_index >= CHV_GPIO_IDX_START_E) {
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gpio_index -= CHV_GPIO_IDX_START_E;
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port = CHV_IOSF_PORT_GPIO_E;
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} else {
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port = CHV_IOSF_PORT_GPIO_N;
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}
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} else {
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/* XXX: The spec is unclear about CHV GPIO on seq v2 */
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if (gpio_source != 0) {
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DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
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return;
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}
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if (gpio_index >= CHV_GPIO_IDX_START_E) {
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DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
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gpio_index);
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return;
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}
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port = CHV_IOSF_PORT_GPIO_N;
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}
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family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
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gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
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cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
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cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
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mutex_lock(&dev_priv->sb_lock);
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vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
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vlv_iosf_sb_write(dev_priv, port, cfg0,
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CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
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CHV_GPIO_GPIOTXSTATE(value));
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mutex_unlock(&dev_priv->sb_lock);
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}
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static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
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u8 gpio_source, u8 gpio_index, bool value)
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{
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/* XXX: this table is a quick ugly hack. */
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static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
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struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
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if (!gpio_desc) {
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gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
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"panel", gpio_index,
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value ? GPIOD_OUT_LOW :
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GPIOD_OUT_HIGH);
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if (IS_ERR_OR_NULL(gpio_desc)) {
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DRM_ERROR("GPIO index %u request failed (%ld)\n",
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gpio_index, PTR_ERR(gpio_desc));
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return;
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}
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bxt_gpio_table[gpio_index] = gpio_desc;
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}
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gpiod_set_value(gpio_desc, value);
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}
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static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
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{
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struct drm_device *dev = intel_dsi->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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u8 gpio_source, gpio_index = 0, gpio_number;
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bool value;
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DRM_DEBUG_KMS("\n");
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if (dev_priv->vbt.dsi.seq_version >= 3)
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gpio_index = *data++;
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gpio_number = *data++;
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/* gpio source in sequence v2 only */
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if (dev_priv->vbt.dsi.seq_version == 2)
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gpio_source = (*data >> 1) & 3;
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else
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gpio_source = 0;
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/* pull up/down */
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value = *data++ & 1;
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if (IS_VALLEYVIEW(dev_priv))
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vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
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else if (IS_CHERRYVIEW(dev_priv))
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chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
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else
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bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
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return data;
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}
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static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
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{
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DRM_DEBUG_KMS("Skipping I2C element execution\n");
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return data + *(data + 6) + 7;
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}
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static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
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{
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DRM_DEBUG_KMS("Skipping SPI element execution\n");
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return data + *(data + 5) + 6;
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}
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static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
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{
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DRM_DEBUG_KMS("Skipping PMIC element execution\n");
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return data + 15;
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}
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typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
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const u8 *data);
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static const fn_mipi_elem_exec exec_elem[] = {
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[MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
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[MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
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[MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
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[MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
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[MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
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[MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
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};
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/*
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* MIPI Sequence from VBT #53 parsing logic
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* We have already separated each seqence during bios parsing
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* Following is generic execution function for any sequence
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*/
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static const char * const seq_name[] = {
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[MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
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[MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
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[MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
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[MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
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[MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
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[MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
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[MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
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[MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
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[MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
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[MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
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[MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
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};
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static const char *sequence_name(enum mipi_seq seq_id)
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{
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if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
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return seq_name[seq_id];
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else
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return "(unknown)";
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}
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void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
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enum mipi_seq seq_id)
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{
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struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
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const u8 *data;
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fn_mipi_elem_exec mipi_elem_exec;
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if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
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return;
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|
|
data = dev_priv->vbt.dsi.sequence[seq_id];
|
|
if (!data)
|
|
return;
|
|
|
|
WARN_ON(*data != seq_id);
|
|
|
|
DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
|
|
seq_id, sequence_name(seq_id));
|
|
|
|
/* Skip Sequence Byte. */
|
|
data++;
|
|
|
|
/* Skip Size of Sequence. */
|
|
if (dev_priv->vbt.dsi.seq_version >= 3)
|
|
data += 4;
|
|
|
|
while (1) {
|
|
u8 operation_byte = *data++;
|
|
u8 operation_size = 0;
|
|
|
|
if (operation_byte == MIPI_SEQ_ELEM_END)
|
|
break;
|
|
|
|
if (operation_byte < ARRAY_SIZE(exec_elem))
|
|
mipi_elem_exec = exec_elem[operation_byte];
|
|
else
|
|
mipi_elem_exec = NULL;
|
|
|
|
/* Size of Operation. */
|
|
if (dev_priv->vbt.dsi.seq_version >= 3)
|
|
operation_size = *data++;
|
|
|
|
if (mipi_elem_exec) {
|
|
const u8 *next = data + operation_size;
|
|
|
|
data = mipi_elem_exec(intel_dsi, data);
|
|
|
|
/* Consistency check if we have size. */
|
|
if (operation_size && data != next) {
|
|
DRM_ERROR("Inconsistent operation size\n");
|
|
return;
|
|
}
|
|
} else if (operation_size) {
|
|
/* We have size, skip. */
|
|
DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
|
|
operation_byte);
|
|
data += operation_size;
|
|
} else {
|
|
/* No size, can't skip without parsing. */
|
|
DRM_ERROR("Unsupported MIPI operation byte %u\n",
|
|
operation_byte);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
|
|
{
|
|
struct intel_connector *connector = intel_dsi->attached_connector;
|
|
struct drm_device *dev = intel_dsi->base.base.dev;
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct drm_display_mode *mode;
|
|
|
|
mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
|
|
if (!mode)
|
|
return 0;
|
|
|
|
mode->type |= DRM_MODE_TYPE_PREFERRED;
|
|
|
|
drm_mode_probed_add(&connector->base, mode);
|
|
|
|
return 1;
|
|
}
|
|
|
|
bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
|
|
{
|
|
struct drm_device *dev = intel_dsi->base.base.dev;
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
|
|
struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
|
|
struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
|
|
u32 bpp;
|
|
u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
|
|
u32 ui_num, ui_den;
|
|
u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
|
|
u32 ths_prepare_ns, tclk_trail_ns;
|
|
u32 tclk_prepare_clkzero, ths_prepare_hszero;
|
|
u32 lp_to_hs_switch, hs_to_lp_switch;
|
|
u32 pclk, computed_ddr;
|
|
u32 mul;
|
|
u16 burst_mode_ratio;
|
|
enum port port;
|
|
|
|
DRM_DEBUG_KMS("\n");
|
|
|
|
intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
|
|
intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
|
|
intel_dsi->lane_count = mipi_config->lane_cnt + 1;
|
|
intel_dsi->pixel_format =
|
|
pixel_format_from_register_bits(
|
|
mipi_config->videomode_color_format << 7);
|
|
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
|
|
|
|
intel_dsi->dual_link = mipi_config->dual_link;
|
|
intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
|
|
intel_dsi->operation_mode = mipi_config->is_cmd_mode;
|
|
intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
|
|
intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
|
|
intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
|
|
intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
|
|
intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
|
|
intel_dsi->init_count = mipi_config->master_init_timer;
|
|
intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
|
|
intel_dsi->video_frmt_cfg_bits =
|
|
mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
|
|
|
|
pclk = mode->clock;
|
|
|
|
/* In dual link mode each port needs half of pixel clock */
|
|
if (intel_dsi->dual_link) {
|
|
pclk = pclk / 2;
|
|
|
|
/* we can enable pixel_overlap if needed by panel. In this
|
|
* case we need to increase the pixelclock for extra pixels
|
|
*/
|
|
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
|
|
pclk += DIV_ROUND_UP(mode->vtotal *
|
|
intel_dsi->pixel_overlap *
|
|
60, 1000);
|
|
}
|
|
}
|
|
|
|
/* Burst Mode Ratio
|
|
* Target ddr frequency from VBT / non burst ddr freq
|
|
* multiply by 100 to preserve remainder
|
|
*/
|
|
if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
|
|
if (mipi_config->target_burst_mode_freq) {
|
|
computed_ddr = (pclk * bpp) / intel_dsi->lane_count;
|
|
|
|
if (mipi_config->target_burst_mode_freq <
|
|
computed_ddr) {
|
|
DRM_ERROR("Burst mode freq is less than computed\n");
|
|
return false;
|
|
}
|
|
|
|
burst_mode_ratio = DIV_ROUND_UP(
|
|
mipi_config->target_burst_mode_freq * 100,
|
|
computed_ddr);
|
|
|
|
pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
|
|
} else {
|
|
DRM_ERROR("Burst mode target is not set\n");
|
|
return false;
|
|
}
|
|
} else
|
|
burst_mode_ratio = 100;
|
|
|
|
intel_dsi->burst_mode_ratio = burst_mode_ratio;
|
|
intel_dsi->pclk = pclk;
|
|
|
|
bitrate = (pclk * bpp) / intel_dsi->lane_count;
|
|
|
|
switch (intel_dsi->escape_clk_div) {
|
|
case 0:
|
|
tlpx_ns = 50;
|
|
break;
|
|
case 1:
|
|
tlpx_ns = 100;
|
|
break;
|
|
|
|
case 2:
|
|
tlpx_ns = 200;
|
|
break;
|
|
default:
|
|
tlpx_ns = 50;
|
|
break;
|
|
}
|
|
|
|
switch (intel_dsi->lane_count) {
|
|
case 1:
|
|
case 2:
|
|
extra_byte_count = 2;
|
|
break;
|
|
case 3:
|
|
extra_byte_count = 4;
|
|
break;
|
|
case 4:
|
|
default:
|
|
extra_byte_count = 3;
|
|
break;
|
|
}
|
|
|
|
/* in Kbps */
|
|
ui_num = NS_KHZ_RATIO;
|
|
ui_den = bitrate;
|
|
|
|
tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
|
|
ths_prepare_hszero = mipi_config->ths_prepare_hszero;
|
|
|
|
/*
|
|
* B060
|
|
* LP byte clock = TLPX/ (8UI)
|
|
*/
|
|
intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
|
|
|
|
/* DDR clock period = 2 * UI
|
|
* UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
|
|
* UI(nsec) = 10^6 / bitrate
|
|
* DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
|
|
* DDR clock count = ns_value / DDR clock period
|
|
*
|
|
* For GEMINILAKE dphy_param_reg will be programmed in terms of
|
|
* HS byte clock count for other platform in HS ddr clock count
|
|
*/
|
|
mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
|
|
ths_prepare_ns = max(mipi_config->ths_prepare,
|
|
mipi_config->tclk_prepare);
|
|
|
|
/* prepare count */
|
|
prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
|
|
|
|
/* exit zero count */
|
|
exit_zero_cnt = DIV_ROUND_UP(
|
|
(ths_prepare_hszero - ths_prepare_ns) * ui_den,
|
|
ui_num * mul
|
|
);
|
|
|
|
/*
|
|
* Exit zero is unified val ths_zero and ths_exit
|
|
* minimum value for ths_exit = 110ns
|
|
* min (exit_zero_cnt * 2) = 110/UI
|
|
* exit_zero_cnt = 55/UI
|
|
*/
|
|
if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
|
|
exit_zero_cnt += 1;
|
|
|
|
/* clk zero count */
|
|
clk_zero_cnt = DIV_ROUND_UP(
|
|
(tclk_prepare_clkzero - ths_prepare_ns)
|
|
* ui_den, ui_num * mul);
|
|
|
|
/* trail count */
|
|
tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
|
|
trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
|
|
|
|
if (prepare_cnt > PREPARE_CNT_MAX ||
|
|
exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
|
|
clk_zero_cnt > CLK_ZERO_CNT_MAX ||
|
|
trail_cnt > TRAIL_CNT_MAX)
|
|
DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
|
|
|
|
if (prepare_cnt > PREPARE_CNT_MAX)
|
|
prepare_cnt = PREPARE_CNT_MAX;
|
|
|
|
if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
|
|
exit_zero_cnt = EXIT_ZERO_CNT_MAX;
|
|
|
|
if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
|
|
clk_zero_cnt = CLK_ZERO_CNT_MAX;
|
|
|
|
if (trail_cnt > TRAIL_CNT_MAX)
|
|
trail_cnt = TRAIL_CNT_MAX;
|
|
|
|
/* B080 */
|
|
intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
|
|
clk_zero_cnt << 8 | prepare_cnt;
|
|
|
|
/*
|
|
* LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
|
|
* + 10UI + Extra Byte Count
|
|
*
|
|
* HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
|
|
* Extra Byte Count is calculated according to number of lanes.
|
|
* High Low Switch Count is the Max of LP to HS and
|
|
* HS to LP switch count
|
|
*
|
|
*/
|
|
tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
|
|
|
|
/* B044 */
|
|
/* FIXME:
|
|
* The comment above does not match with the code */
|
|
lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
|
|
exit_zero_cnt * 2 + 10, 8);
|
|
|
|
hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
|
|
|
|
intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
|
|
intel_dsi->hs_to_lp_count += extra_byte_count;
|
|
|
|
/* B088 */
|
|
/* LP -> HS for clock lanes
|
|
* LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
|
|
* extra byte count
|
|
* 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
|
|
* 2(in UI) + extra byte count
|
|
* In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
|
|
* 8 + extra byte count
|
|
*/
|
|
intel_dsi->clk_lp_to_hs_count =
|
|
DIV_ROUND_UP(
|
|
4 * tlpx_ui + prepare_cnt * 2 +
|
|
clk_zero_cnt * 2,
|
|
8);
|
|
|
|
intel_dsi->clk_lp_to_hs_count += extra_byte_count;
|
|
|
|
/* HS->LP for Clock Lanes
|
|
* Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
|
|
* Extra byte count
|
|
* 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
|
|
* In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
|
|
* Extra byte count
|
|
*/
|
|
intel_dsi->clk_hs_to_lp_count =
|
|
DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
|
|
8);
|
|
intel_dsi->clk_hs_to_lp_count += extra_byte_count;
|
|
|
|
DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
|
|
DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
|
|
DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count);
|
|
DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
|
|
DRM_DEBUG_KMS("Video mode format %s\n",
|
|
intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
|
|
"non-burst with sync pulse" :
|
|
intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
|
|
"non-burst with sync events" :
|
|
intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
|
|
"burst" : "<unknown>");
|
|
DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
|
|
DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val);
|
|
DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt));
|
|
DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop));
|
|
DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
|
|
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
|
|
DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
|
|
else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
|
|
DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
|
|
else
|
|
DRM_DEBUG_KMS("Dual link: NONE\n");
|
|
DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
|
|
DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
|
|
DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
|
|
DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
|
|
DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
|
|
DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
|
|
DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
|
|
DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
|
|
DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
|
|
DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
|
|
DRM_DEBUG_KMS("BTA %s\n",
|
|
enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
|
|
|
|
/* delays in VBT are in unit of 100us, so need to convert
|
|
* here in ms
|
|
* Delay (100us) * 100 /1000 = Delay / 10 (ms) */
|
|
intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
|
|
intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
|
|
intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
|
|
intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
|
|
intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
|
|
|
|
/* a regular driver would get the device in probe */
|
|
for_each_dsi_port(port, intel_dsi->ports) {
|
|
mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
|
|
}
|
|
|
|
return true;
|
|
}
|