![Tvrtko Ursulin](/assets/img/avatar_default.png)
This removes the usage of intel_ring_emit in favour of directly writing to the ring buffer. intel_ring_emit was preventing the compiler for optimising fetch and increment of the current ring buffer pointer and therefore generating very verbose code for every write. It had no useful purpose since all ringbuffer operations are started and ended with intel_ring_begin and intel_ring_advance respectively, with no bail out in the middle possible, so it is fine to increment the tail in intel_ring_begin and let the code manage the pointer itself. Useless instruction removal amounts to approximately two and half kilobytes of saved text on my build. Not sure if this has any measurable performance implications but executing a ton of useless instructions on fast paths cannot be good. v2: * Change return from intel_ring_begin to error pointer by popular demand. * Move tail increment to intel_ring_advance to enable some error checking. v3: * Move tail advance back into intel_ring_begin. * Rebase and tidy. v4: * Complete rebase after a few months since v3. v5: * Remove unecessary cast and fix !debug compile. (Chris Wilson) v6: * Make intel_ring_offset take request as well. * Fix recording of request postfix plus a sprinkle of asserts. (Chris Wilson) v7: * Use intel_ring_offset to get the postfix. (Chris Wilson) * Convert GVT code as well. v8: * Rename *out++ to *cs++. v9: * Fix GVT out to cs conversion in GVT. v10: * Rebase for new intel_ring_begin in selftests. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170214113242.29241-1-tvrtko.ursulin@linux.intel.com
453 lines
13 KiB
C
453 lines
13 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions: *
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "intel_mocs.h"
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#include "intel_lrc.h"
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#include "intel_ringbuffer.h"
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/* structures required */
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struct drm_i915_mocs_entry {
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u32 control_value;
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u16 l3cc_value;
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};
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struct drm_i915_mocs_table {
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u32 size;
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const struct drm_i915_mocs_entry *table;
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};
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/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
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#define LE_CACHEABILITY(value) ((value) << 0)
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#define LE_TGT_CACHE(value) ((value) << 2)
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#define LE_LRUM(value) ((value) << 4)
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#define LE_AOM(value) ((value) << 6)
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#define LE_RSC(value) ((value) << 7)
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#define LE_SCC(value) ((value) << 8)
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#define LE_PFM(value) ((value) << 11)
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#define LE_SCF(value) ((value) << 14)
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/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
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#define L3_ESC(value) ((value) << 0)
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#define L3_SCC(value) ((value) << 1)
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#define L3_CACHEABILITY(value) ((value) << 4)
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/* Helper defines */
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#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
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/* (e)LLC caching options */
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#define LE_PAGETABLE 0
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#define LE_UC 1
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#define LE_WT 2
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#define LE_WB 3
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/* L3 caching options */
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#define L3_DIRECT 0
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#define L3_UC 1
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#define L3_RESERVED 2
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#define L3_WB 3
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/* Target cache */
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#define LE_TC_PAGETABLE 0
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#define LE_TC_LLC 1
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#define LE_TC_LLC_ELLC 2
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#define LE_TC_LLC_ELLC_ALT 3
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/*
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* MOCS tables
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*
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* These are the MOCS tables that are programmed across all the rings.
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* The control value is programmed to all the rings that support the
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* MOCS registers. While the l3cc_values are only programmed to the
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* LNCFCMOCS0 - LNCFCMOCS32 registers.
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*
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* These tables are intended to be kept reasonably consistent across
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* platforms. However some of the fields are not applicable to all of
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* them.
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*
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* Entries not part of the following tables are undefined as far as
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* userspace is concerned and shouldn't be relied upon. For the time
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* being they will be implicitly initialized to the strictest caching
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* configuration (uncached) to guarantee forwards compatibility with
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* userspace programs written against more recent kernels providing
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* additional MOCS entries.
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*
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* NOTE: These tables MUST start with being uncached and the length
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* MUST be less than 63 as the last two registers are reserved
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* by the hardware. These tables are part of the kernel ABI and
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* may only be updated incrementally by adding entries at the
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* end.
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*/
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static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
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[I915_MOCS_UNCACHED] = {
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/* 0x00000009 */
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.control_value = LE_CACHEABILITY(LE_UC) |
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LE_TGT_CACHE(LE_TC_LLC_ELLC) |
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LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
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LE_PFM(0) | LE_SCF(0),
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/* 0x0010 */
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.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
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},
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[I915_MOCS_PTE] = {
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/* 0x00000038 */
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.control_value = LE_CACHEABILITY(LE_PAGETABLE) |
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LE_TGT_CACHE(LE_TC_LLC_ELLC) |
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LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
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LE_PFM(0) | LE_SCF(0),
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/* 0x0030 */
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.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
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},
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[I915_MOCS_CACHED] = {
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/* 0x0000003b */
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.control_value = LE_CACHEABILITY(LE_WB) |
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LE_TGT_CACHE(LE_TC_LLC_ELLC) |
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LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
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LE_PFM(0) | LE_SCF(0),
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/* 0x0030 */
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.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
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},
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};
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/* NOTE: the LE_TGT_CACHE is not used on Broxton */
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static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
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[I915_MOCS_UNCACHED] = {
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/* 0x00000009 */
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.control_value = LE_CACHEABILITY(LE_UC) |
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LE_TGT_CACHE(LE_TC_LLC_ELLC) |
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LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
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LE_PFM(0) | LE_SCF(0),
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/* 0x0010 */
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.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
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},
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[I915_MOCS_PTE] = {
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/* 0x00000038 */
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.control_value = LE_CACHEABILITY(LE_PAGETABLE) |
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LE_TGT_CACHE(LE_TC_LLC_ELLC) |
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LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
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LE_PFM(0) | LE_SCF(0),
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/* 0x0030 */
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.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
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},
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[I915_MOCS_CACHED] = {
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/* 0x00000039 */
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.control_value = LE_CACHEABILITY(LE_UC) |
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LE_TGT_CACHE(LE_TC_LLC_ELLC) |
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LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
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LE_PFM(0) | LE_SCF(0),
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/* 0x0030 */
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.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
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},
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};
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/**
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* get_mocs_settings()
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* @dev_priv: i915 device.
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* @table: Output table that will be made to point at appropriate
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* MOCS values for the device.
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*
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* This function will return the values of the MOCS table that needs to
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* be programmed for the platform. It will return the values that need
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* to be programmed and if they need to be programmed.
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*
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* Return: true if there are applicable MOCS settings for the device.
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*/
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static bool get_mocs_settings(struct drm_i915_private *dev_priv,
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struct drm_i915_mocs_table *table)
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{
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bool result = false;
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if (IS_GEN9_BC(dev_priv)) {
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table->size = ARRAY_SIZE(skylake_mocs_table);
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table->table = skylake_mocs_table;
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result = true;
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} else if (IS_GEN9_LP(dev_priv)) {
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table->size = ARRAY_SIZE(broxton_mocs_table);
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table->table = broxton_mocs_table;
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result = true;
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} else {
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WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
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"Platform that should have a MOCS table does not.\n");
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}
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/* WaDisableSkipCaching:skl,bxt,kbl,glk */
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if (IS_GEN9(dev_priv)) {
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int i;
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for (i = 0; i < table->size; i++)
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if (WARN_ON(table->table[i].l3cc_value &
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(L3_ESC(1) | L3_SCC(0x7))))
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return false;
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}
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return result;
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}
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static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
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{
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switch (engine_id) {
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case RCS:
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return GEN9_GFX_MOCS(index);
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case VCS:
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return GEN9_MFX0_MOCS(index);
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case BCS:
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return GEN9_BLT_MOCS(index);
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case VECS:
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return GEN9_VEBOX_MOCS(index);
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case VCS2:
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return GEN9_MFX1_MOCS(index);
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default:
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MISSING_CASE(engine_id);
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return INVALID_MMIO_REG;
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}
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}
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/**
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* intel_mocs_init_engine() - emit the mocs control table
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* @engine: The engine for whom to emit the registers.
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*
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* This function simply emits a MI_LOAD_REGISTER_IMM command for the
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* given table starting at the given address.
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*
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* Return: 0 on success, otherwise the error status.
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*/
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int intel_mocs_init_engine(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct drm_i915_mocs_table table;
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unsigned int index;
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if (!get_mocs_settings(dev_priv, &table))
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return 0;
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if (WARN_ON(table.size > GEN9_NUM_MOCS_ENTRIES))
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return -ENODEV;
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for (index = 0; index < table.size; index++)
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I915_WRITE(mocs_register(engine->id, index),
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table.table[index].control_value);
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/*
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* Ok, now set the unused entries to uncached. These entries
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* are officially undefined and no contract for the contents
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* and settings is given for these entries.
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*
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* Entry 0 in the table is uncached - so we are just writing
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* that value to all the used entries.
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*/
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for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
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I915_WRITE(mocs_register(engine->id, index),
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table.table[0].control_value);
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return 0;
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}
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/**
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* emit_mocs_control_table() - emit the mocs control table
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* @req: Request to set up the MOCS table for.
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* @table: The values to program into the control regs.
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*
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* This function simply emits a MI_LOAD_REGISTER_IMM command for the
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* given table starting at the given address.
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*
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* Return: 0 on success, otherwise the error status.
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*/
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static int emit_mocs_control_table(struct drm_i915_gem_request *req,
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const struct drm_i915_mocs_table *table)
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{
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enum intel_engine_id engine = req->engine->id;
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unsigned int index;
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u32 *cs;
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if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
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return -ENODEV;
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cs = intel_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES);
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for (index = 0; index < table->size; index++) {
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*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
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*cs++ = table->table[index].control_value;
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}
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/*
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* Ok, now set the unused entries to uncached. These entries
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* are officially undefined and no contract for the contents
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* and settings is given for these entries.
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*
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* Entry 0 in the table is uncached - so we are just writing
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* that value to all the used entries.
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*/
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for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
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*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
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*cs++ = table->table[0].control_value;
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}
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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return 0;
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}
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static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
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u16 low,
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u16 high)
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{
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return table->table[low].l3cc_value |
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table->table[high].l3cc_value << 16;
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}
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/**
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* emit_mocs_l3cc_table() - emit the mocs control table
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* @req: Request to set up the MOCS table for.
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* @table: The values to program into the control regs.
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*
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* This function simply emits a MI_LOAD_REGISTER_IMM command for the
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* given table starting at the given address. This register set is
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* programmed in pairs.
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*
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* Return: 0 on success, otherwise the error status.
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*/
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static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
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const struct drm_i915_mocs_table *table)
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{
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unsigned int i;
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u32 *cs;
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if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
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return -ENODEV;
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cs = intel_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2);
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for (i = 0; i < table->size/2; i++) {
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*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
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*cs++ = l3cc_combine(table, 2 * i, 2 * i + 1);
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}
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if (table->size & 0x01) {
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/* Odd table size - 1 left over */
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*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
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*cs++ = l3cc_combine(table, 2 * i, 0);
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i++;
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}
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/*
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* Now set the rest of the table to uncached - use entry 0 as
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* this will be uncached. Leave the last pair uninitialised as
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* they are reserved by the hardware.
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*/
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for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
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*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
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*cs++ = l3cc_combine(table, 0, 0);
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}
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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return 0;
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}
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/**
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* intel_mocs_init_l3cc_table() - program the mocs control table
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* @dev_priv: i915 device private
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*
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* This function simply programs the mocs registers for the given table
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* starting at the given address. This register set is programmed in pairs.
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*
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* These registers may get programmed more than once, it is simpler to
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* re-program 32 registers than maintain the state of when they were programmed.
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* We are always reprogramming with the same values and this only on context
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* start.
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*
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* Return: Nothing.
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*/
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void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_mocs_table table;
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unsigned int i;
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if (!get_mocs_settings(dev_priv, &table))
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return;
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for (i = 0; i < table.size/2; i++)
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I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 2*i+1));
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/* Odd table size - 1 left over */
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if (table.size & 0x01) {
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I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 0));
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i++;
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}
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/*
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* Now set the rest of the table to uncached - use entry 0 as
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* this will be uncached. Leave the last pair as initialised as
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* they are reserved by the hardware.
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*/
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for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++)
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I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0));
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}
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/**
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* intel_rcs_context_init_mocs() - program the MOCS register.
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* @req: Request to set up the MOCS tables for.
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*
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* This function will emit a batch buffer with the values required for
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* programming the MOCS register values for all the currently supported
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* rings.
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*
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* These registers are partially stored in the RCS context, so they are
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* emitted at the same time so that when a context is created these registers
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* are set up. These registers have to be emitted into the start of the
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* context as setting the ELSP will re-init some of these registers back
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* to the hw values.
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*
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* Return: 0 on success, otherwise the error status.
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*/
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int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
|
|
{
|
|
struct drm_i915_mocs_table t;
|
|
int ret;
|
|
|
|
if (get_mocs_settings(req->i915, &t)) {
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|
/* Program the RCS control registers */
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|
ret = emit_mocs_control_table(req, &t);
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|
if (ret)
|
|
return ret;
|
|
|
|
/* Now program the l3cc registers */
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|
ret = emit_mocs_l3cc_table(req, &t);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|