![Tony Lindgren](/assets/img/avatar_default.png)
For omap15xx and 730 we need to use the MPU timer as the 32K timer is not available. For omap16xx we want to use the 32K timer because of PM. Fix this by allowing to build in both timers. Signed-off-by: Tony Lindgren <tony@atomide.com>
194 lines
5.6 KiB
C
194 lines
5.6 KiB
C
/*
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* linux/arch/arm/mach-omap1/timer32k.c
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*
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* OMAP 32K Timer
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*
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* Copyright (C) 2004 - 2005 Nokia Corporation
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* Partial timer rewrite and additional dynamic tick timer support by
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* Tony Lindgen <tony@atomide.com> and
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* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* OMAP Dual-mode timer framework support by Timo Teras
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*
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* MPU timer code based on the older MPU timer code for OMAP
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* Copyright (C) 2000 RidgeRun, Inc.
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* Author: Greg Lonnon <glonnon@ridgerun.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <mach/hardware.h>
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#include <asm/leds.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <plat/common.h>
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#include <plat/dmtimer.h>
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/*
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* ---------------------------------------------------------------------------
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* 32KHz OS timer
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*
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* This currently works only on 16xx, as 1510 does not have the continuous
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* 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
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* of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
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* on 1510 would be possible, but the timer would not be as accurate as
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* with the 32KHz synchronized timer.
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* ---------------------------------------------------------------------------
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*/
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/* 16xx specific defines */
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#define OMAP1_32K_TIMER_BASE 0xfffb9000
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#define OMAP1_32K_TIMER_CR 0x08
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#define OMAP1_32K_TIMER_TVR 0x00
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#define OMAP1_32K_TIMER_TCR 0x04
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#define OMAP_32K_TICKS_PER_SEC (32768)
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/*
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* TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
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* so with HZ = 128, TVR = 255.
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*/
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#define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
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#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
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(((nr_jiffies) * (clock_rate)) / HZ)
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static inline void omap_32k_timer_write(int val, int reg)
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{
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omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
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}
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static inline unsigned long omap_32k_timer_read(int reg)
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{
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return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
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}
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static inline void omap_32k_timer_start(unsigned long load_val)
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{
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if (!load_val)
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load_val = 1;
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omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
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omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
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}
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static inline void omap_32k_timer_stop(void)
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{
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omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
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}
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#define omap_32k_timer_ack_irq()
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static int omap_32k_timer_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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omap_32k_timer_start(delta);
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return 0;
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}
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static void omap_32k_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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omap_32k_timer_stop();
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static struct clock_event_device clockevent_32k_timer = {
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.name = "32k-timer",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_next_event = omap_32k_timer_set_next_event,
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.set_mode = omap_32k_timer_set_mode,
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};
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static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_32k_timer;
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omap_32k_timer_ack_irq();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction omap_32k_timer_irq = {
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.name = "32KHz timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = omap_32k_timer_interrupt,
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};
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static __init void omap_init_32k_timer(void)
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{
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setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
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clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
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NSEC_PER_SEC,
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clockevent_32k_timer.shift);
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clockevent_32k_timer.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
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clockevent_32k_timer.min_delta_ns =
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clockevent_delta2ns(1, &clockevent_32k_timer);
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clockevent_32k_timer.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_32k_timer);
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}
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/*
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* ---------------------------------------------------------------------------
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* Timer initialization
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* ---------------------------------------------------------------------------
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*/
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bool __init omap_32k_timer_init(void)
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{
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omap_init_clocksource_32k();
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#ifdef CONFIG_OMAP_DM_TIMER
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omap_dm_timer_init();
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#endif
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omap_init_32k_timer();
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return true;
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}
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