135 lines
3.7 KiB
C
135 lines
3.7 KiB
C
/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dal_asic_id.h"
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#include "dc_types.h"
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#include "dccg.h"
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#include "clk_mgr_internal.h"
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#include "dce100/dce_clk_mgr.h"
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#include "dce110/dce110_clk_mgr.h"
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#include "dce112/dce112_clk_mgr.h"
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#include "dce120/dce120_clk_mgr.h"
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#include "dcn10/rv1_clk_mgr.h"
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#include "dcn10/rv2_clk_mgr.h"
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int clk_mgr_helper_get_active_display_cnt(
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struct dc *dc,
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struct dc_state *context)
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{
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int i, display_count;
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display_count = 0;
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for (i = 0; i < context->stream_count; i++) {
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const struct dc_stream_state *stream = context->streams[i];
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/*
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* Only notify active stream or virtual stream.
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* Need to notify virtual stream to work around
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* headless case. HPD does not fire when system is in
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* S0i2.
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*/
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if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
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display_count++;
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}
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return display_count;
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}
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struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
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{
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struct hw_asic_id asic_id = ctx->asic_id;
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struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
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if (clk_mgr == NULL) {
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BREAK_TO_DEBUGGER();
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return NULL;
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}
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switch (asic_id.chip_family) {
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case FAMILY_CI:
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case FAMILY_KV:
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dce_clk_mgr_construct(ctx, clk_mgr);
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break;
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case FAMILY_CZ:
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dce110_clk_mgr_construct(ctx, clk_mgr);
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break;
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case FAMILY_VI:
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if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
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ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
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dce_clk_mgr_construct(ctx, clk_mgr);
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break;
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}
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if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
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ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
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ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
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dce112_clk_mgr_construct(ctx, clk_mgr);
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break;
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}
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if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
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dce112_clk_mgr_construct(ctx, clk_mgr);
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break;
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}
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break;
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case FAMILY_AI:
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if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
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dce121_clk_mgr_construct(ctx, clk_mgr);
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else
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dce120_clk_mgr_construct(ctx, clk_mgr);
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break;
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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case FAMILY_RV:
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if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
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rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
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break;
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}
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if (ASICREV_IS_RAVEN(asic_id.hw_internal_rev) ||
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ASICREV_IS_PICASSO(asic_id.hw_internal_rev)) {
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rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
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break;
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}
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break;
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#endif /* Family RV */
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default:
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ASSERT(0); /* Unknown Asic */
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break;
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}
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return &clk_mgr->base;
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}
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void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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kfree(clk_mgr);
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}
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