![]() Make sure that when doing a lock() or an unlock() operation we don't clear the QE bit from Status Register 2. JESD216 revB or later offers information about the *default* Status Register commands to use (see BFPT DWORDS[15], bits 22:20). In this standard, Status Register 1 refers to the first data byte transferred on a Read Status (05h) or Write Status (01h) command. Status register 2 refers to the byte read using instruction 35h. Status register 2 is the second byte transferred in a Write Status (01h) command. Industry naming and definitions of these Status Registers may differ. The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20. There are cases in which writing only one byte to the Status Register 1 has the side-effect of clearing Status Register 2 and implicitly the Quad Enable bit. This side-effect is hit just by the BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> |
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.. | ||
bbm.h | ||
blktrans.h | ||
cfi.h | ||
cfi_endian.h | ||
concat.h | ||
doc2000.h | ||
flashchip.h | ||
ftl.h | ||
gen_probe.h | ||
hyperbus.h | ||
inftl.h | ||
jedec.h | ||
latch-addr-flash.h | ||
lpc32xx_mlc.h | ||
lpc32xx_slc.h | ||
map.h | ||
mtd.h | ||
mtdram.h | ||
nand-gpio.h | ||
nand.h | ||
nand_bch.h | ||
nand_ecc.h | ||
ndfc.h | ||
nftl.h | ||
onenand.h | ||
onenand_regs.h | ||
onfi.h | ||
partitions.h | ||
pfow.h | ||
physmap.h | ||
pismo.h | ||
plat-ram.h | ||
platnand.h | ||
qinfo.h | ||
rawnand.h | ||
sh_flctl.h | ||
sharpsl.h | ||
spear_smi.h | ||
spi-nor.h | ||
spinand.h | ||
super.h | ||
ubi.h | ||
xip.h |