39d9b85a4d
Since BIOS RC 1.4 it would enable CDCLK PLL during BIOS S3 resume, then driver needs to set CDCLK to avoid display corruption if DPLL0 enabled. References: https://bugs.freedesktop.org/show_bug.cgi?id=91697 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Cooper Chiou <cooper.chiou@intel.com> Reviewed-by: Wei Shun Chang <wei.shun.chang@intel.com> Tested-by: Gary Wang <gary.c.wang@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Gavin Hindman <gavin.hindman@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Xiong Y Zhang <xiong.y.zhang@intel.com> Signed-off-by: Gary Wang <gary.c.wang@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> |
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| drm | ||
| host1x | ||
| ipu-v3 | ||
| vga | ||
| Makefile | ||