22 lines
768 B
JSON
22 lines
768 B
JSON
[
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{
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"PublicDescription": "The number of core clock cycles"
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"ArchStdEvent": "CPU_CYCLES",
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"BriefDescription": "The number of core clock cycles."
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},
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{
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"PublicDescription": "This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR.",
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"ArchStdEvent": "BUS_ACCESS",
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},
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{
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"PublicDescription": "This event duplicates CPU_CYCLES."
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"ArchStdEvent": "BUS_CYCLES",
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},
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{
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"ArchStdEvent": "BUS_ACCESS_RD",
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},
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{
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"ArchStdEvent": "BUS_ACCESS_WR",
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}
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]
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