![Rafał Miłecki](/assets/img/avatar_default.png)
We will need method of selecting encoder that should receive HDMI block. For now we assign HDMI block to first enabled encoder. Hopefully there are not many RS6x0 chips with two digital encoders. [airlied: add RS740 checks as per Alex suggestion.] Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
586 lines
17 KiB
C
586 lines
17 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Christian König.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon.h"
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#include "atom.h"
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/*
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* HDMI color format
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*/
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enum r600_hdmi_color_format {
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RGB = 0,
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YCC_422 = 1,
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YCC_444 = 2
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};
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/*
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* IEC60958 status bits
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*/
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enum r600_hdmi_iec_status_bits {
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AUDIO_STATUS_DIG_ENABLE = 0x01,
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AUDIO_STATUS_V = 0x02,
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AUDIO_STATUS_VCFG = 0x04,
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AUDIO_STATUS_EMPHASIS = 0x08,
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AUDIO_STATUS_COPYRIGHT = 0x10,
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AUDIO_STATUS_NONAUDIO = 0x20,
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AUDIO_STATUS_PROFESSIONAL = 0x40,
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AUDIO_STATUS_LEVEL = 0x80
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};
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struct {
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uint32_t Clock;
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int N_32kHz;
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int CTS_32kHz;
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int N_44_1kHz;
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int CTS_44_1kHz;
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int N_48kHz;
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int CTS_48kHz;
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} r600_hdmi_ACR[] = {
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/* 32kHz 44.1kHz 48kHz */
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/* Clock N CTS N CTS N CTS */
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{ 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
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{ 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
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{ 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
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{ 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
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{ 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
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{ 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
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{ 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
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{ 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
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{ 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
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{ 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
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{ 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
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};
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/*
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* calculate CTS value if it's not found in the table
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*/
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static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq)
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{
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if (*CTS == 0)
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*CTS = clock * N / (128 * freq) * 1000;
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DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
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N, *CTS, freq);
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}
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/*
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* update the N and CTS parameters for a given pixel clock rate
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*/
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static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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int CTS;
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int N;
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int i;
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for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++);
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CTS = r600_hdmi_ACR[i].CTS_32kHz;
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N = r600_hdmi_ACR[i].N_32kHz;
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r600_hdmi_calc_CTS(clock, &CTS, N, 32000);
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WREG32(offset+R600_HDMI_32kHz_CTS, CTS << 12);
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WREG32(offset+R600_HDMI_32kHz_N, N);
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CTS = r600_hdmi_ACR[i].CTS_44_1kHz;
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N = r600_hdmi_ACR[i].N_44_1kHz;
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r600_hdmi_calc_CTS(clock, &CTS, N, 44100);
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WREG32(offset+R600_HDMI_44_1kHz_CTS, CTS << 12);
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WREG32(offset+R600_HDMI_44_1kHz_N, N);
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CTS = r600_hdmi_ACR[i].CTS_48kHz;
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N = r600_hdmi_ACR[i].N_48kHz;
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r600_hdmi_calc_CTS(clock, &CTS, N, 48000);
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WREG32(offset+R600_HDMI_48kHz_CTS, CTS << 12);
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WREG32(offset+R600_HDMI_48kHz_N, N);
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}
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/*
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* calculate the crc for a given info frame
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*/
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static void r600_hdmi_infoframe_checksum(uint8_t packetType,
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uint8_t versionNumber,
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uint8_t length,
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uint8_t *frame)
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{
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int i;
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frame[0] = packetType + versionNumber + length;
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for (i = 1; i <= length; i++)
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frame[0] += frame[i];
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frame[0] = 0x100 - frame[0];
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}
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/*
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* build a HDMI Video Info Frame
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*/
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static void r600_hdmi_videoinfoframe(
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struct drm_encoder *encoder,
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enum r600_hdmi_color_format color_format,
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int active_information_present,
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uint8_t active_format_aspect_ratio,
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uint8_t scan_information,
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uint8_t colorimetry,
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uint8_t ex_colorimetry,
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uint8_t quantization,
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int ITC,
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uint8_t picture_aspect_ratio,
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uint8_t video_format_identification,
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uint8_t pixel_repetition,
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uint8_t non_uniform_picture_scaling,
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uint8_t bar_info_data_valid,
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uint16_t top_bar,
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uint16_t bottom_bar,
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uint16_t left_bar,
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uint16_t right_bar
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)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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uint8_t frame[14];
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frame[0x0] = 0;
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frame[0x1] =
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(scan_information & 0x3) |
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((bar_info_data_valid & 0x3) << 2) |
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((active_information_present & 0x1) << 4) |
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((color_format & 0x3) << 5);
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frame[0x2] =
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(active_format_aspect_ratio & 0xF) |
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((picture_aspect_ratio & 0x3) << 4) |
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((colorimetry & 0x3) << 6);
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frame[0x3] =
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(non_uniform_picture_scaling & 0x3) |
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((quantization & 0x3) << 2) |
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((ex_colorimetry & 0x7) << 4) |
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((ITC & 0x1) << 7);
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frame[0x4] = (video_format_identification & 0x7F);
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frame[0x5] = (pixel_repetition & 0xF);
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frame[0x6] = (top_bar & 0xFF);
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frame[0x7] = (top_bar >> 8);
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frame[0x8] = (bottom_bar & 0xFF);
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frame[0x9] = (bottom_bar >> 8);
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frame[0xA] = (left_bar & 0xFF);
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frame[0xB] = (left_bar >> 8);
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frame[0xC] = (right_bar & 0xFF);
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frame[0xD] = (right_bar >> 8);
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r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
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WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0,
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frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
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WREG32(offset+R600_HDMI_VIDEOINFOFRAME_1,
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frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
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WREG32(offset+R600_HDMI_VIDEOINFOFRAME_2,
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frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
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WREG32(offset+R600_HDMI_VIDEOINFOFRAME_3,
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frame[0xC] | (frame[0xD] << 8));
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}
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/*
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* build a Audio Info Frame
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*/
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static void r600_hdmi_audioinfoframe(
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struct drm_encoder *encoder,
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uint8_t channel_count,
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uint8_t coding_type,
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uint8_t sample_size,
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uint8_t sample_frequency,
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uint8_t format,
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uint8_t channel_allocation,
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uint8_t level_shift,
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int downmix_inhibit
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)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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uint8_t frame[11];
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frame[0x0] = 0;
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frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4);
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frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2);
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frame[0x3] = format;
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frame[0x4] = channel_allocation;
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frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7);
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frame[0x6] = 0;
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frame[0x7] = 0;
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frame[0x8] = 0;
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frame[0x9] = 0;
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frame[0xA] = 0;
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r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame);
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WREG32(offset+R600_HDMI_AUDIOINFOFRAME_0,
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frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
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WREG32(offset+R600_HDMI_AUDIOINFOFRAME_1,
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frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
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}
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/*
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* test if audio buffer is filled enough to start playing
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*/
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static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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return (RREG32(offset+R600_HDMI_STATUS) & 0x10) != 0;
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}
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/*
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* have buffer status changed since last call?
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*/
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int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
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{
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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int status, result;
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if (!radeon_encoder->hdmi_offset)
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return 0;
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status = r600_hdmi_is_audio_buffer_filled(encoder);
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result = radeon_encoder->hdmi_buffer_status != status;
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radeon_encoder->hdmi_buffer_status = status;
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return result;
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}
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/*
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* write the audio workaround status to the hardware
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*/
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void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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uint32_t offset = radeon_encoder->hdmi_offset;
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if (!offset)
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return;
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if (!radeon_encoder->hdmi_audio_workaround ||
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r600_hdmi_is_audio_buffer_filled(encoder)) {
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/* disable audio workaround */
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WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001);
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} else {
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/* enable audio workaround */
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WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001);
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}
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}
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/*
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* update the info frames with the data from the current display mode
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*/
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void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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if (ASIC_IS_DCE4(rdev))
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return;
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if (!offset)
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return;
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r600_audio_set_clock(encoder, mode->clock);
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WREG32(offset+R600_HDMI_UNKNOWN_0, 0x1000);
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WREG32(offset+R600_HDMI_UNKNOWN_1, 0x0);
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WREG32(offset+R600_HDMI_UNKNOWN_2, 0x1000);
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r600_hdmi_update_ACR(encoder, mode->clock);
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WREG32(offset+R600_HDMI_VIDEOCNTL, 0x13);
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WREG32(offset+R600_HDMI_VERSION, 0x202);
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r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
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/* it's unknown what these bits do excatly, but it's indeed quite usefull for debugging */
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WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF);
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WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF);
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WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001);
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WREG32(offset+R600_HDMI_AUDIO_DEBUG_3, 0x00000001);
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r600_hdmi_audio_workaround(encoder);
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/* audio packets per line, does anyone know how to calc this ? */
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WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000);
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}
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/*
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* update settings with current parameters from audio engine
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*/
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void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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int channels = r600_audio_channels(rdev);
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int rate = r600_audio_rate(rdev);
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int bps = r600_audio_bits_per_sample(rdev);
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uint8_t status_bits = r600_audio_status_bits(rdev);
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uint8_t category_code = r600_audio_category_code(rdev);
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uint32_t iec;
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if (!offset)
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return;
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DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
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r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
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channels, rate, bps);
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DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
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(int)status_bits, (int)category_code);
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iec = 0;
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if (status_bits & AUDIO_STATUS_PROFESSIONAL)
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iec |= 1 << 0;
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if (status_bits & AUDIO_STATUS_NONAUDIO)
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iec |= 1 << 1;
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if (status_bits & AUDIO_STATUS_COPYRIGHT)
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iec |= 1 << 2;
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if (status_bits & AUDIO_STATUS_EMPHASIS)
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iec |= 1 << 3;
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iec |= category_code << 8;
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switch (rate) {
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case 32000: iec |= 0x3 << 24; break;
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case 44100: iec |= 0x0 << 24; break;
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case 88200: iec |= 0x8 << 24; break;
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case 176400: iec |= 0xc << 24; break;
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case 48000: iec |= 0x2 << 24; break;
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case 96000: iec |= 0xa << 24; break;
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case 192000: iec |= 0xe << 24; break;
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}
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WREG32(offset+R600_HDMI_IEC60958_1, iec);
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iec = 0;
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switch (bps) {
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case 16: iec |= 0x2; break;
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case 20: iec |= 0x3; break;
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case 24: iec |= 0xb; break;
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}
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if (status_bits & AUDIO_STATUS_V)
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iec |= 0x5 << 16;
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WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f);
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/* 0x021 or 0x031 sets the audio frame length */
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WREG32(offset+R600_HDMI_AUDIOCNTL, 0x31);
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r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0);
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r600_hdmi_audio_workaround(encoder);
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}
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static int r600_hdmi_find_free_block(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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struct drm_encoder *encoder;
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struct radeon_encoder *radeon_encoder;
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bool free_blocks[3] = { true, true, true };
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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radeon_encoder = to_radeon_encoder(encoder);
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switch (radeon_encoder->hdmi_offset) {
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case R600_HDMI_BLOCK1:
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free_blocks[0] = false;
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break;
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case R600_HDMI_BLOCK2:
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free_blocks[1] = false;
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break;
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case R600_HDMI_BLOCK3:
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free_blocks[2] = false;
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break;
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}
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}
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if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 ||
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rdev->family == CHIP_RS740) {
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return free_blocks[0] ? R600_HDMI_BLOCK1 : 0;
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} else if (rdev->family >= CHIP_R600) {
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if (free_blocks[0])
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return R600_HDMI_BLOCK1;
|
|
else if (free_blocks[1])
|
|
return R600_HDMI_BLOCK2;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void r600_hdmi_assign_block(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
|
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
|
|
|
|
if (!dig) {
|
|
dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n");
|
|
return;
|
|
}
|
|
|
|
if (ASIC_IS_DCE4(rdev)) {
|
|
/* TODO */
|
|
} else if (ASIC_IS_DCE3(rdev)) {
|
|
radeon_encoder->hdmi_offset = dig->dig_encoder ?
|
|
R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1;
|
|
if (ASIC_IS_DCE32(rdev))
|
|
radeon_encoder->hdmi_config_offset = dig->dig_encoder ?
|
|
R600_HDMI_CONFIG2 : R600_HDMI_CONFIG1;
|
|
} else if (rdev->family >= CHIP_R600 || rdev->family == CHIP_RS600 ||
|
|
rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
|
|
radeon_encoder->hdmi_offset = r600_hdmi_find_free_block(dev);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* enable the HDMI engine
|
|
*/
|
|
void r600_hdmi_enable(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
|
uint32_t offset;
|
|
|
|
if (ASIC_IS_DCE4(rdev))
|
|
return;
|
|
|
|
if (!radeon_encoder->hdmi_offset) {
|
|
r600_hdmi_assign_block(encoder);
|
|
if (!radeon_encoder->hdmi_offset) {
|
|
dev_warn(rdev->dev, "Could not find HDMI block for "
|
|
"0x%x encoder\n", radeon_encoder->encoder_id);
|
|
return;
|
|
}
|
|
}
|
|
|
|
offset = radeon_encoder->hdmi_offset;
|
|
if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) {
|
|
WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1);
|
|
} else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
|
|
switch (radeon_encoder->encoder_id) {
|
|
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
|
|
WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4);
|
|
WREG32(offset + R600_HDMI_ENABLE, 0x101);
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
|
|
WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4);
|
|
WREG32(offset + R600_HDMI_ENABLE, 0x105);
|
|
break;
|
|
default:
|
|
dev_err(rdev->dev, "Unknown HDMI output type\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (rdev->irq.installed
|
|
&& rdev->family != CHIP_RS600
|
|
&& rdev->family != CHIP_RS690
|
|
&& rdev->family != CHIP_RS740) {
|
|
|
|
/* if irq is available use it */
|
|
rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true;
|
|
radeon_irq_set(rdev);
|
|
|
|
r600_audio_disable_polling(encoder);
|
|
} else {
|
|
/* if not fallback to polling */
|
|
r600_audio_enable_polling(encoder);
|
|
}
|
|
|
|
DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
|
|
radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
|
|
}
|
|
|
|
/*
|
|
* disable the HDMI engine
|
|
*/
|
|
void r600_hdmi_disable(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
|
uint32_t offset;
|
|
|
|
if (ASIC_IS_DCE4(rdev))
|
|
return;
|
|
|
|
offset = radeon_encoder->hdmi_offset;
|
|
if (!offset) {
|
|
dev_err(rdev->dev, "Disabling not enabled HDMI\n");
|
|
return;
|
|
}
|
|
|
|
DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
|
|
offset, radeon_encoder->encoder_id);
|
|
|
|
/* disable irq */
|
|
rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = false;
|
|
radeon_irq_set(rdev);
|
|
|
|
/* disable polling */
|
|
r600_audio_disable_polling(encoder);
|
|
|
|
if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) {
|
|
WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1);
|
|
} else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
|
|
switch (radeon_encoder->encoder_id) {
|
|
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
|
|
WREG32_P(AVIVO_TMDSA_CNTL, 0, ~0x4);
|
|
WREG32(offset + R600_HDMI_ENABLE, 0);
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
|
|
WREG32_P(AVIVO_LVTMA_CNTL, 0, ~0x4);
|
|
WREG32(offset + R600_HDMI_ENABLE, 0);
|
|
break;
|
|
default:
|
|
dev_err(rdev->dev, "Unknown HDMI output type\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
radeon_encoder->hdmi_offset = 0;
|
|
radeon_encoder->hdmi_config_offset = 0;
|
|
}
|