![Nathan Chancellor](/assets/img/avatar_default.png)
This satisfies a checkpatch.pl warning and is the preferred method for notating the license due to its lack of ambiguity. Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
291 lines
8 KiB
C
291 lines
8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2016 Realtek Corporation.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDMANTDIV_H__
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#define __PHYDMANTDIV_H__
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/* 2.0 2014.11.04
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* 2.1 2015.01.13 Dino
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* 2.2 2015.01.16 Dino
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* 3.1 2015.07.29 YuChen, remove 92c 92d 8723a
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* 3.2 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B
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* 3.3 2015.08.12 Stanley. 8723B does not need to check the antenna is control
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* by BT, because antenna diversity only works when BT is disable
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* or radio off
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* 3.4 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna
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* Diversity
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* 3.5 2015.10.07 Stanley Always check antenna detection result from BT-coex.
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* for 8723B, not from PHYDM
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* 3.6 2015.11.16 Stanley
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* 3.7 2015.11.20 Dino Add SmartAnt FAT Patch
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* 3.8 2015.12.21 Dino, Add SmartAnt dynamic training packet num
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* 3.9 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and
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* add cmd for adjust truth table
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*/
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#define ANTDIV_VERSION "3.9"
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/* 1 ============================================================
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* 1 Definition
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* 1 ============================================================
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*/
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#define ANTDIV_INIT 0xff
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#define MAIN_ANT 1 /*ant A or ant Main or S1*/
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#define AUX_ANT 2 /*AntB or ant Aux or S0*/
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#define MAX_ANT 3 /* 3 for AP using*/
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#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D,
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* TX fixed at S1
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*/
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#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D,
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* TX fixed at S1
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*/
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/*smart antenna*/
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#define SUPPORT_RF_PATH_NUM 4
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#define SUPPORT_BEAM_PATTERN_NUM 4
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#define NUM_ANTENNA_8821A 2
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#define SUPPORT_BEAM_SET_PATTERN_NUM 8
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#define NO_FIX_TX_ANT 0
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#define FIX_TX_AT_MAIN 1
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#define FIX_AUX_AT_MAIN 2
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/* Antenna Diversty Control type */
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#define ODM_AUTO_ANT 0
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#define ODM_FIX_MAIN_ANT 1
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#define ODM_FIX_AUX_ANT 2
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#define ODM_N_ANTDIV_SUPPORT \
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(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | \
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ODM_RTL8723D | ODM_RTL8195A)
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#define ODM_AC_ANTDIV_SUPPORT \
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(ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | \
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ODM_RTL8822B | ODM_RTL8814B)
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#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
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#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
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#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
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#define ODM_ANTDIV_2G_SUPPORT_IC \
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(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | \
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ODM_RTL8188F | ODM_RTL8723D)
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#define ODM_ANTDIV_5G_SUPPORT_IC \
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(ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
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#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
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#define ODM_ANTDIV_2G BIT(0)
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#define ODM_ANTDIV_5G BIT(1)
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#define ANTDIV_ON 1
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#define ANTDIV_OFF 0
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#define FAT_ON 1
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#define FAT_OFF 0
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#define TX_BY_DESC 1
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#define TX_BY_REG 0
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#define RSSI_METHOD 0
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#define EVM_METHOD 1
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#define CRC32_METHOD 2
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#define INIT_ANTDIV_TIMMER 0
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#define CANCEL_ANTDIV_TIMMER 1
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#define RELEASE_ANTDIV_TIMMER 2
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#define CRC32_FAIL 1
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#define CRC32_OK 0
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#define evm_rssi_th_high 25
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#define evm_rssi_th_low 20
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#define NORMAL_STATE_MIAN 1
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#define NORMAL_STATE_AUX 2
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#define TRAINING_STATE 3
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#define FORCE_RSSI_DIFF 10
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#define CSI_ON 1
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#define CSI_OFF 0
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#define DIVON_CSIOFF 1
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#define DIVOFF_CSION 2
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#define BDC_DIV_TRAIN_STATE 0
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#define bdc_bfer_train_state 1
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#define BDC_DECISION_STATE 2
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#define BDC_BF_HOLD_STATE 3
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#define BDC_DIV_HOLD_STATE 4
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#define BDC_MODE_1 1
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#define BDC_MODE_2 2
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#define BDC_MODE_3 3
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#define BDC_MODE_4 4
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#define BDC_MODE_NULL 0xff
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/*SW S0S1 antenna diversity*/
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#define SWAW_STEP_INIT 0xff
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#define SWAW_STEP_PEEK 0
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#define SWAW_STEP_DETERMINE 1
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#define RSSI_CHECK_RESET_PERIOD 10
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#define RSSI_CHECK_THRESHOLD 50
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/*Hong Lin Smart antenna*/
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#define HL_SMTANT_2WIRE_DATA_LEN 24
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/* 1 ============================================================
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* 1 structure
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* 1 ============================================================
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*/
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struct sw_antenna_switch {
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u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD",
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*than check this antenna again
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*/
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u8 try_flag;
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s32 pre_rssi;
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u8 cur_antenna;
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u8 pre_antenna;
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u8 rssi_trying;
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u8 reset_idx;
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u8 train_time;
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u8 train_time_flag; /*base on RSSI difference between two antennas*/
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struct timer_list phydm_sw_antenna_switch_timer;
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u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
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bool is_sw_ant_div_by_ctrl_frame;
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/* AntDect (Before link Antenna Switch check) need to be moved*/
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u16 single_ant_counter;
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u16 dual_ant_counter;
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u16 aux_fail_detec_counter;
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u16 retry_counter;
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u8 swas_no_link_state;
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u32 swas_no_link_bk_reg948;
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bool ANTA_ON; /*To indicate ant A is or not*/
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bool ANTB_ON; /*To indicate ant B is on or not*/
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bool pre_aux_fail_detec;
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bool rssi_ant_dect_result;
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u8 ant_5g;
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u8 ant_2g;
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};
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struct fast_antenna_training {
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u8 bssid[6];
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u8 antsel_rx_keep_0;
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u8 antsel_rx_keep_1;
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u8 antsel_rx_keep_2;
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u8 antsel_rx_keep_3;
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u32 ant_sum_rssi[7];
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u32 ant_rssi_cnt[7];
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u32 ant_ave_rssi[7];
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u8 fat_state;
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u32 train_idx;
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u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
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u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
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u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
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u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
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u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
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u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
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u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
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u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
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u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
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u8 rx_idle_ant;
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u8 ant_div_on_off;
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bool is_become_linked;
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u32 min_max_rssi;
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u8 idx_ant_div_counter_2g;
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u8 idx_ant_div_counter_5g;
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u8 ant_div_2g_5g;
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u32 cck_ctrl_frame_cnt_main;
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u32 cck_ctrl_frame_cnt_aux;
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u32 ofdm_ctrl_frame_cnt_main;
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u32 ofdm_ctrl_frame_cnt_aux;
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u32 main_ant_ctrl_frame_sum;
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u32 aux_ant_ctrl_frame_sum;
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u32 main_ant_ctrl_frame_cnt;
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u32 aux_ant_ctrl_frame_cnt;
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u8 b_fix_tx_ant;
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bool fix_ant_bfee;
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bool enable_ctrl_frame_antdiv;
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bool use_ctrl_frame_antdiv;
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u8 hw_antsw_occur;
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u8 *p_force_tx_ant_by_desc;
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u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's
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*outer parameter later
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*/
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u8 *p_default_s0_s1;
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u8 default_s0_s1;
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};
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/* 1 ============================================================
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* 1 enumeration
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* 1 ============================================================
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*/
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/*Fast antenna training*/
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enum fat_state {
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FAT_BEFORE_LINK_STATE = 0,
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FAT_PREPARE_STATE = 1,
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FAT_TRAINING_STATE = 2,
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FAT_DECISION_STATE = 3
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};
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enum ant_div_type {
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NO_ANTDIV = 0xFF,
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CG_TRX_HW_ANTDIV = 0x01,
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CGCS_RX_HW_ANTDIV = 0x02,
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FIXED_HW_ANTDIV = 0x03,
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CG_TRX_SMART_ANTDIV = 0x04,
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CGCS_RX_SW_ANTDIV = 0x05,
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/*8723B intrnal switch S0 S1*/
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S0S1_SW_ANTDIV = 0x06,
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/*TRX S0S1 diversity for 8723D*/
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S0S1_TRX_HW_ANTDIV = 0x07,
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/*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and
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*each ant. is equipped with 4 antenna patterns
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*/
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HL_SW_SMART_ANT_TYPE1 = 0x10,
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/*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
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HL_SW_SMART_ANT_TYPE2 = 0x11,
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};
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/* 1 ============================================================
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* 1 function prototype
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* 1 ============================================================
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*/
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void odm_stop_antenna_switch_dm(void *dm_void);
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void phydm_enable_antenna_diversity(void *dm_void);
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void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
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);
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#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
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void odm_sw_ant_div_rest_after_link(void *dm_void);
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void odm_ant_div_reset(void *dm_void);
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void odm_antenna_diversity_init(void *dm_void);
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void odm_antenna_diversity(void *dm_void);
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#endif /*#ifndef __ODMANTDIV_H__*/
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