99 lines
1.8 KiB
YAML
99 lines
1.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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# Copyright 2020 NXP
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/fsl,imx8mp-lvds-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8MP LVDS PHY Device Tree Bindings
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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description: |
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LVDS PHY found on i.MX8MP SoC. The IP block contains two PHYs, each of
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which supports a four data lane LVDS channel.
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properties:
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compatible:
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enum:
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- fsl,imx8mp-lvds-phy
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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gpr:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to block control syscon
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: apb
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port@0:
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type: object
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description: A port node pointing to the PHY instance0's port node
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properties:
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reg:
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maxItems: 1
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description: PHY instance number.
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"#phy-cells":
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const: 0
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required:
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- reg
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- "#phy-cells"
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port@1:
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type: object
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description: A port node pointing to the PHY instance1's port node
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properties:
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reg:
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maxItems: 1
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description: PHY instance number
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"#phy-cells":
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const: 0
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required:
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- reg
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- "#phy-cells"
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required:
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- compatible
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- "#address-cells"
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- "#size-cells"
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- gpr
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- port@0
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- port@1
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additionalProperties: false
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examples:
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- |
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ldb_phy: phy@32ec0128 {
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compatible = "fsl,imx8mp-lvds-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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gpr = <&mediamix_blk_ctl>;
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clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
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clock-names = "apb";
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ldb_phy1: port@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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ldb_phy2: port@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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};
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...
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